On 07/19/2012 12:35 AM, Eric Anholt wrote:
> This thread count is only supposed to be enabled when "WIZ Hashing Disable in
> GT_MODE register enabled." I've always been confused whether that means the
> bit in the register should be 1 or 0. For my IVB GT2's register 0x7008 value
> of 0x0, this appears to work fine.
>
> Improves l4d2 performance at 640x480 by 0.88 +/- 0.11% (n=88). Improves
> performance with rasterization at 1280x1024 by 1.45% +/- 0.36% (n=6).
> ---
> src/mesa/drivers/dri/i965/brw_context.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c
> b/src/mesa/drivers/dri/i965/brw_context.c
> index f5c8b6e..5a109e3 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -248,7 +248,7 @@ brwCreateContext(int api,
> brw->urb.max_vs_entries = 512;
> brw->urb.max_gs_entries = 192;
> } else if (intel->gt == 2) {
> - brw->max_wm_threads = 86;
> + brw->max_wm_threads = 172;
> brw->max_vs_threads = 128;
> brw->max_gs_threads = 128;
> brw->urb.size = 256;
Glad to see this.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
With my Sandybridge GT2's register 0x20d0 value of 0x0, bumping the
maximum thread count to 80 also seems to work (Unigine Heaven didn't
tank my system). I haven't done any performance measurements.
It's unclear to me what the right values should be for the GT1 parts.
The documentation is pretty hard to follow. It'd be nice to be able to
bump those too, if it's legal to do so.
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