Reviewed-by: Marek Olšák <[email protected]> Marek
On Tue, Jun 18, 2019 at 12:20 PM Haehnle, Nicolai <[email protected]> wrote: > Makes sense to me. > > Acked-by: Nicolai Hähnle <[email protected]> > > -----Original Message----- > From: Connor Abbott <[email protected]> > Sent: Dienstag, 18. Juni 2019 15:21 > To: [email protected] > Cc: Marek Olšák <[email protected]>; Haehnle, Nicolai < > [email protected]>; Connor Abbott <[email protected]> > Subject: [PATCH] ac,radeonsi: Always mark buffer stores as > inaccessiblememonly > > inaccessiblememonly means that it doesn't modify memory accesible via > normal LLVM pointers. This lets LLVM's dead store elimination, memcpy > forwarding, etc. ignore functions with this attribute. We don't represent > descriptors as pointers, so this property is always true of buffer and > image stores. There are plans to represent descriptors via pointers, but > this just means that now nothing is inaccessiblememonly, as LLVM will then > understand loads/stores via its usual alias analysis. > > Radeonsi was mistakenly only setting it if the driver could prove that > there were no reads, and then it was cargo-culted into ac_llvm_build and > ac_llvm_to_nir. Rip it out of everything. > > statistics with nir enabled: > > Totals from affected shaders: > SGPRS: 152 -> 152 (0.00 %) > VGPRS: 128 -> 132 (3.12 %) > Spilled SGPRs: 0 -> 0 (0.00 %) > Spilled VGPRs: 0 -> 0 (0.00 %) > Private memory VGPRs: 0 -> 0 (0.00 %) > Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 9324 -> 9244 > (-0.86 %) bytes > LDS: 2 -> 2 (0.00 %) blocks > Max Waves: 17 -> 17 (0.00 %) > Wait states: 0 -> 0 (0.00 %) > > The only difference was a manhattan31 shader. > > Acked-by: Timothy Arceri <[email protected]> > --- > > I included this in > https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1018 since it was > related to my goal of making sure that the NIR code added all the > attributes that the TGSI code does for buffer stores/loads, but I'm sending > it here for visibility since it affects the old paths too and involves some > LLVM knowledge. > > src/amd/common/ac_llvm_build.c | 61 +++++++------------ > src/amd/common/ac_llvm_build.h | 16 ++--- > src/amd/common/ac_llvm_util.h | 7 --- > src/amd/common/ac_nir_to_llvm.c | 12 ++-- > src/amd/vulkan/radv_nir_to_llvm.c | 20 +++--- > .../radeonsi/si_compute_prim_discard.c | 4 +- > src/gallium/drivers/radeonsi/si_shader.c | 26 ++++---- > .../drivers/radeonsi/si_shader_tgsi_mem.c | 8 +-- > 8 files changed, 61 insertions(+), 93 deletions(-) > > diff --git a/src/amd/common/ac_llvm_build.c > b/src/amd/common/ac_llvm_build.c index b93fdde023e..1e6247ad72e 100644 > --- a/src/amd/common/ac_llvm_build.c > +++ b/src/amd/common/ac_llvm_build.c > @@ -1116,7 +1116,6 @@ ac_build_llvm7_buffer_store_common(struct > ac_llvm_context *ctx, > unsigned num_channels, > bool glc, > bool slc, > - bool writeonly_memory, > bool use_format) > { > LLVMValueRef args[] = { > @@ -1141,7 +1140,7 @@ ac_build_llvm7_buffer_store_common(struct > ac_llvm_context *ctx, > } > > ac_build_intrinsic(ctx, name, ctx->voidt, args, ARRAY_SIZE(args), > - ac_get_store_intr_attribs(writeonly_memory)); > + AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY); > } > > static void > @@ -1155,7 +1154,6 @@ ac_build_llvm8_buffer_store_common(struct > ac_llvm_context *ctx, > LLVMTypeRef return_channel_type, > bool glc, > bool slc, > - bool writeonly_memory, > bool use_format, > bool structurized) > { > @@ -1184,7 +1182,7 @@ ac_build_llvm8_buffer_store_common(struct > ac_llvm_context *ctx, > } > > ac_build_intrinsic(ctx, name, ctx->voidt, args, idx, > - ac_get_store_intr_attribs(writeonly_memory)); > + AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY); > } > > void > @@ -1195,18 +1193,17 @@ ac_build_buffer_store_format(struct > ac_llvm_context *ctx, > LLVMValueRef voffset, > unsigned num_channels, > bool glc, > - bool slc, > - bool writeonly_memory) > + bool slc) > { > if (HAVE_LLVM >= 0x800) { > ac_build_llvm8_buffer_store_common(ctx, rsrc, data, vindex, > voffset, NULL, > num_channels, > ctx->f32, glc, slc, > - writeonly_memory, true, > true); > + true, true); > } else { > ac_build_llvm7_buffer_store_common(ctx, rsrc, data, > vindex, voffset, > num_channels, glc, slc, > - writeonly_memory, true); > + true); > } > } > > @@ -1224,7 +1221,6 @@ ac_build_buffer_store_dword(struct ac_llvm_context > *ctx, > unsigned inst_offset, > bool glc, > bool slc, > - bool writeonly_memory, > bool swizzle_enable_hint) > { > /* Split 3 channel stores, because only LLVM 9+ support 3-channel > @@ -1240,11 +1236,11 @@ ac_build_buffer_store_dword(struct ac_llvm_context > *ctx, > > ac_build_buffer_store_dword(ctx, rsrc, v01, 2, voffset, > soffset, inst_offset, glc, slc, > - writeonly_memory, > swizzle_enable_hint); > + swizzle_enable_hint); > ac_build_buffer_store_dword(ctx, rsrc, v[2], 1, voffset, > soffset, inst_offset + 8, > glc, slc, > - writeonly_memory, > swizzle_enable_hint); > + swizzle_enable_hint); > return; > } > > @@ -1267,7 +1263,6 @@ ac_build_buffer_store_dword(struct ac_llvm_context > *ctx, > num_channels, > ctx->f32, > glc, slc, > - > writeonly_memory, > false, false); > } else { > if (voffset) > @@ -1277,7 +1272,7 @@ ac_build_buffer_store_dword(struct ac_llvm_context > *ctx, > > ac_to_float(ctx, vdata), > ctx->i32_0, > offset, > num_channels, > glc, slc, > - > writeonly_memory, false); > + false); > } > return; > } > @@ -1294,7 +1289,7 @@ ac_build_buffer_store_dword(struct ac_llvm_context > *ctx, > > ac_build_raw_tbuffer_store(ctx, rsrc, vdata, voffset, soffset, > immoffset, num_channels, dfmt, nfmt, > glc, > - slc, writeonly_memory); > + slc); > } > > static LLVMValueRef > @@ -2000,7 +1995,6 @@ ac_build_llvm8_tbuffer_store(struct ac_llvm_context > *ctx, > unsigned nfmt, > bool glc, > bool slc, > - bool writeonly_memory, > bool structurized) > { > LLVMValueRef args[7]; > @@ -2024,7 +2018,7 @@ ac_build_llvm8_tbuffer_store(struct ac_llvm_context > *ctx, > indexing_kind, type_name); > > ac_build_intrinsic(ctx, name, ctx->voidt, args, idx, > - ac_get_store_intr_attribs(writeonly_memory)); > + AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY); > } > > static void > @@ -2040,7 +2034,6 @@ ac_build_tbuffer_store(struct ac_llvm_context *ctx, > unsigned nfmt, > bool glc, > bool slc, > - bool writeonly_memory, > bool structurized) /* only matters for LLVM 8+ */ { > if (HAVE_LLVM >= 0x800) { > @@ -2050,8 +2043,7 @@ ac_build_tbuffer_store(struct ac_llvm_context *ctx, > > ac_build_llvm8_tbuffer_store(ctx, rsrc, vdata, vindex, > voffset, > soffset, num_channels, dfmt, > nfmt, > - glc, slc, writeonly_memory, > - structurized); > + glc, slc, structurized); > } else { > LLVMValueRef params[] = { > vdata, > @@ -2073,7 +2065,7 @@ ac_build_tbuffer_store(struct ac_llvm_context *ctx, > type_names[func]); > > ac_build_intrinsic(ctx, name, ctx->voidt, params, 10, > - > ac_get_store_intr_attribs(writeonly_memory)); > + AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY); > } > } > > @@ -2089,12 +2081,11 @@ ac_build_struct_tbuffer_store(struct > ac_llvm_context *ctx, > unsigned dfmt, > unsigned nfmt, > bool glc, > - bool slc, > - bool writeonly_memory) > + bool slc) > { > ac_build_tbuffer_store(ctx, rsrc, vdata, vindex, voffset, soffset, > immoffset, num_channels, dfmt, nfmt, glc, > slc, > - writeonly_memory, true); > + true); > } > > void > @@ -2108,12 +2099,11 @@ ac_build_raw_tbuffer_store(struct ac_llvm_context > *ctx, > unsigned dfmt, > unsigned nfmt, > bool glc, > - bool slc, > - bool writeonly_memory) > + bool slc) > { > ac_build_tbuffer_store(ctx, rsrc, vdata, NULL, voffset, soffset, > immoffset, num_channels, dfmt, nfmt, glc, > slc, > - writeonly_memory, false); > + false); > } > > void > @@ -2122,8 +2112,7 @@ ac_build_tbuffer_store_short(struct ac_llvm_context > *ctx, > LLVMValueRef vdata, > LLVMValueRef voffset, > LLVMValueRef soffset, > - bool glc, > - bool writeonly_memory) > + bool glc) > { > vdata = LLVMBuildBitCast(ctx->builder, vdata, ctx->i16, ""); > > @@ -2132,8 +2121,7 @@ ac_build_tbuffer_store_short(struct ac_llvm_context > *ctx, > ac_build_llvm8_buffer_store_common(ctx, rsrc, vdata, NULL, > voffset, soffset, 1, > ctx->i16, glc, false, > - writeonly_memory, false, > - false); > + false, false); > } else { > unsigned dfmt = V_008F0C_BUF_DATA_FORMAT_16; > unsigned nfmt = V_008F0C_BUF_NUM_FORMAT_UINT; @@ -2141,8 > +2129,8 @@ ac_build_tbuffer_store_short(struct ac_llvm_context *ctx, > vdata = LLVMBuildZExt(ctx->builder, vdata, ctx->i32, ""); > > ac_build_raw_tbuffer_store(ctx, rsrc, vdata, voffset, > soffset, > - ctx->i32_0, 1, dfmt, nfmt, glc, > false, > - writeonly_memory); > + ctx->i32_0, 1, dfmt, nfmt, glc, > + false); > } > } > > @@ -2152,8 +2140,7 @@ ac_build_tbuffer_store_byte(struct ac_llvm_context > *ctx, > LLVMValueRef vdata, > LLVMValueRef voffset, > LLVMValueRef soffset, > - bool glc, > - bool writeonly_memory) > + bool glc) > { > vdata = LLVMBuildBitCast(ctx->builder, vdata, ctx->i8, ""); > > @@ -2162,8 +2149,7 @@ ac_build_tbuffer_store_byte(struct ac_llvm_context > *ctx, > ac_build_llvm8_buffer_store_common(ctx, rsrc, vdata, NULL, > voffset, soffset, 1, > ctx->i8, glc, false, > - writeonly_memory, false, > - false); > + false, false); > } else { > unsigned dfmt = V_008F0C_BUF_DATA_FORMAT_8; > unsigned nfmt = V_008F0C_BUF_NUM_FORMAT_UINT; @@ -2171,8 > +2157,7 @@ ac_build_tbuffer_store_byte(struct ac_llvm_context *ctx, > vdata = LLVMBuildZExt(ctx->builder, vdata, ctx->i32, ""); > > ac_build_raw_tbuffer_store(ctx, rsrc, vdata, voffset, > soffset, > - ctx->i32_0, 1, dfmt, nfmt, glc, > false, > - writeonly_memory); > + ctx->i32_0, 1, dfmt, nfmt, glc, > false); > } > } > /** > diff --git a/src/amd/common/ac_llvm_build.h > b/src/amd/common/ac_llvm_build.h index bbdb01184e6..a1654d2b2c4 100644 > --- a/src/amd/common/ac_llvm_build.h > +++ b/src/amd/common/ac_llvm_build.h > @@ -271,7 +271,6 @@ ac_build_buffer_store_dword(struct ac_llvm_context > *ctx, > unsigned inst_offset, > bool glc, > bool slc, > - bool writeonly_memory, > bool swizzle_enable_hint); > > void > @@ -282,8 +281,7 @@ ac_build_buffer_store_format(struct ac_llvm_context > *ctx, > LLVMValueRef voffset, > unsigned num_channels, > bool glc, > - bool slc, > - bool writeonly_memory); > + bool slc); > > LLVMValueRef > ac_build_buffer_load(struct ac_llvm_context *ctx, @@ -395,8 +393,7 @@ > ac_build_tbuffer_store_short(struct ac_llvm_context *ctx, > LLVMValueRef vdata, > LLVMValueRef voffset, > LLVMValueRef soffset, > - bool glc, > - bool writeonly_memory); > + bool glc); > > void > ac_build_tbuffer_store_byte(struct ac_llvm_context *ctx, @@ -404,8 +401,7 > @@ ac_build_tbuffer_store_byte(struct ac_llvm_context *ctx, > LLVMValueRef vdata, > LLVMValueRef voffset, > LLVMValueRef soffset, > - bool glc, > - bool writeonly_memory); > + bool glc); > > void > ac_build_struct_tbuffer_store(struct ac_llvm_context *ctx, @@ -419,8 > +415,7 @@ ac_build_struct_tbuffer_store(struct ac_llvm_context *ctx, > unsigned dfmt, > unsigned nfmt, > bool glc, > - bool slc, > - bool writeonly_memory); > + bool slc); > > void > ac_build_raw_tbuffer_store(struct ac_llvm_context *ctx, @@ -433,8 +428,7 > @@ ac_build_raw_tbuffer_store(struct ac_llvm_context *ctx, > unsigned dfmt, > unsigned nfmt, > bool glc, > - bool slc, > - bool writeonly_memory); > + bool slc); > > LLVMValueRef > ac_get_thread_id(struct ac_llvm_context *ctx); diff --git > a/src/amd/common/ac_llvm_util.h b/src/amd/common/ac_llvm_util.h index > e1840b6f0a3..d2e3c85cfab 100644 > --- a/src/amd/common/ac_llvm_util.h > +++ b/src/amd/common/ac_llvm_util.h > @@ -120,13 +120,6 @@ ac_get_load_intr_attribs(bool can_speculate) > AC_FUNC_ATTR_READONLY; > } > > -static inline unsigned > -ac_get_store_intr_attribs(bool writeonly_memory) -{ > - return writeonly_memory ? AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY : > - AC_FUNC_ATTR_WRITEONLY; > -} > - > unsigned > ac_count_scratch_private_memory(LLVMValueRef function); > > diff --git a/src/amd/common/ac_nir_to_llvm.c > b/src/amd/common/ac_nir_to_llvm.c index f26e74cb63e..b73a0f599f1 100644 > --- a/src/amd/common/ac_nir_to_llvm.c > +++ b/src/amd/common/ac_nir_to_llvm.c > @@ -1622,13 +1622,11 @@ static void visit_store_ssbo(struct ac_nir_context > *ctx, > if (num_bytes == 1) { > ac_build_tbuffer_store_byte(&ctx->ac, rsrc, data, > offset, ctx->ac.i32_0, > - cache_policy & ac_glc, > - writeonly_memory); > + cache_policy & ac_glc); > } else if (num_bytes == 2) { > ac_build_tbuffer_store_short(&ctx->ac, rsrc, data, > offset, ctx->ac.i32_0, > - cache_policy & ac_glc, > - writeonly_memory); > + cache_policy & > ac_glc); > } else { > int num_channels = num_bytes / 4; > > @@ -1654,8 +1652,7 @@ static void visit_store_ssbo(struct ac_nir_context > *ctx, > num_channels, offset, > ctx->ac.i32_0, 0, > cache_policy & ac_glc, > - false, > writeonly_memory, > - false); > + false, false); > } > } > } > @@ -2556,8 +2553,7 @@ static void visit_image_store(struct ac_nir_context > *ctx, > > ac_build_buffer_store_format(&ctx->ac, rsrc, src, vindex, > ctx->ac.i32_0, src_channels, > - args.cache_policy & ac_glc, > false, > - writeonly_memory); > + args.cache_policy & ac_glc, > false); > } else { > args.opcode = ac_image_store; > args.data[0] = ac_to_float(&ctx->ac, get_src(ctx, > instr->src[3])); diff --git a/src/amd/vulkan/radv_nir_to_llvm.c > b/src/amd/vulkan/radv_nir_to_llvm.c > index 755b7cb0246..d6f286fe4ec 100644 > --- a/src/amd/vulkan/radv_nir_to_llvm.c > +++ b/src/amd/vulkan/radv_nir_to_llvm.c > @@ -1585,13 +1585,13 @@ store_tcs_output(struct ac_shader_abi *abi, > if (!is_tess_factor && writemask != 0xF) > ac_build_buffer_store_dword(&ctx->ac, > ctx->hs_ring_tess_offchip, value, 1, > buf_addr, ctx->oc_lds, > - 4 * (base + chan), 1, > 0, true, false); > + 4 * (base + chan), 1, > 0, false); > } > > if (writemask == 0xF) { > ac_build_buffer_store_dword(&ctx->ac, > ctx->hs_ring_tess_offchip, src, 4, > buf_addr, ctx->oc_lds, > - (base * 4), 1, 0, true, false); > + (base * 4), 1, 0, false); > } > } > > @@ -1858,7 +1858,7 @@ visit_emit_vertex(struct ac_shader_abi *abi, > unsigned stream, LLVMValueRef *addr > ctx->gsvs_ring[stream], > out_val, 1, > voffset, > ctx->gs2vs_offset, 0, > - 1, 1, true, true); > + 1, 1, true); > } > } > > @@ -2773,7 +2773,7 @@ radv_emit_stream_output(struct radv_shader_context > *ctx, > ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf], > vdata, num_comps, > so_write_offsets[buf], > ctx->ac.i32_0, offset, > - 1, 1, true, false); > + 1, 1, false); > } > > static void > @@ -3150,7 +3150,7 @@ handle_es_outputs_post(struct radv_shader_context > *ctx, > out_val, 1, > NULL, > ctx->es2gs_offset, > (4 * > param_index + j) * 4, > - 1, 1, true, > true); > + 1, 1, true); > } > } > } > @@ -3283,7 +3283,7 @@ write_tess_factors(struct radv_shader_context *ctx) > ac_build_buffer_store_dword(&ctx->ac, buffer, > LLVMConstInt(ctx->ac.i32, > 0x80000000, false), > 1, ctx->ac.i32_0, tf_base, > - 0, 1, 0, true, false); > + 0, 1, 0, false); > tf_offset += 4; > > ac_nir_build_endif(&inner_if_ctx); > @@ -3292,11 +3292,11 @@ write_tess_factors(struct radv_shader_context *ctx) > /* Store the tessellation factors. */ > ac_build_buffer_store_dword(&ctx->ac, buffer, vec0, > MIN2(stride, 4), byteoffset, tf_base, > - tf_offset, 1, 0, true, false); > + tf_offset, 1, 0, false); > if (vec1) > ac_build_buffer_store_dword(&ctx->ac, buffer, vec1, > stride - 4, byteoffset, > tf_base, > - 16 + tf_offset, 1, 0, true, > false); > + 16 + tf_offset, 1, 0, false); > > //store to offchip for TES to read - only if TES reads them > if (ctx->options->key.tcs.tes_reads_tess_factors) { @@ -3313,7 > +3313,7 @@ write_tess_factors(struct radv_shader_context *ctx) > > ac_build_buffer_store_dword(&ctx->ac, > ctx->hs_ring_tess_offchip, outer_vec, > outer_comps, tf_outer_offset, > - ctx->oc_lds, 0, 1, 0, true, > false); > + ctx->oc_lds, 0, 1, 0, false); > if (inner_comps) { > param_inner = > shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER); > tf_inner_offset = get_tcs_tes_buffer_address(ctx, > NULL, @@ -3323,7 +3323,7 @@ write_tess_factors(struct radv_shader_context > *ctx) > ac_build_gather_values(&ctx->ac, inner, > inner_comps); > ac_build_buffer_store_dword(&ctx->ac, > ctx->hs_ring_tess_offchip, inner_vec, > inner_comps, > tf_inner_offset, > - ctx->oc_lds, 0, 1, 0, > true, false); > + ctx->oc_lds, 0, 1, 0, > false); > } > } > ac_nir_build_endif(&if_ctx); > diff --git a/src/gallium/drivers/radeonsi/si_compute_prim_discard.c > b/src/gallium/drivers/radeonsi/si_compute_prim_discard.c > index 3bed818d5ad..0f2934243a1 100644 > --- a/src/gallium/drivers/radeonsi/si_compute_prim_discard.c > +++ b/src/gallium/drivers/radeonsi/si_compute_prim_discard.c > @@ -811,7 +811,7 @@ void si_build_prim_discard_compute_shader(struct > si_shader_context *ctx) > }; > LLVMValueRef rsrc = > ac_build_gather_values(&ctx->ac, desc, 4); > ac_build_buffer_store_dword(&ctx->ac, rsrc, count, > 1, ctx->i32_0, > - ctx->i32_0, 0, true, > true, true, false); > + ctx->i32_0, 0, true, > true, false); > } else { > LLVMBuildStore(builder, count, > si_expand_32bit_pointer(ctx, > vertex_count_addr)); @@ -864,7 +864,7 @@ void > si_build_prim_discard_compute_shader(struct si_shader_context *ctx) > > ac_build_buffer_store_format(&ctx->ac, output_indexbuf, > vdata, > vindex, ctx->i32_0, 3, true, > - INDEX_STORES_USE_SLC, true); > + INDEX_STORES_USE_SLC); > } > lp_build_endif(&if_accepted); > > diff --git a/src/gallium/drivers/radeonsi/si_shader.c > b/src/gallium/drivers/radeonsi/si_shader.c > index 92c68f21459..1f4954c43bf 100644 > --- a/src/gallium/drivers/radeonsi/si_shader.c > +++ b/src/gallium/drivers/radeonsi/si_shader.c > @@ -1351,7 +1351,7 @@ static void store_output_tcs(struct > lp_build_tgsi_context *bld_base, > if (reg->Register.WriteMask != 0xF && !is_tess_factor) { > ac_build_buffer_store_dword(&ctx->ac, buffer, > value, 1, > buf_addr, base, > - 4 * chan_index, 1, 0, > true, false); > + 4 * chan_index, 1, 0, > false); > } > > /* Write tess factors into VGPRs for the epilog. */ @@ > -1371,7 +1371,7 @@ static void store_output_tcs(struct > lp_build_tgsi_context *bld_base, > LLVMValueRef value = ac_build_gather_values(&ctx->ac, > values, 4); > ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, > buf_addr, > - base, 0, 1, 0, true, false); > + base, 0, 1, 0, false); > } > } > > @@ -1479,7 +1479,7 @@ static void si_nir_store_output_tcs(struct > ac_shader_abi *abi, > ac_build_buffer_store_dword(&ctx->ac, buffer, > value, 1, > addr, base, > 4 * > buffer_store_offset, > - 1, 0, true, false); > + 1, 0, false); > } > > /* Write tess factors into VGPRs for the epilog. */ @@ > -1499,7 +1499,7 @@ static void si_nir_store_output_tcs(struct ac_shader_abi > *abi, > LLVMValueRef value = ac_build_gather_values(&ctx->ac, > values, 4); > ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, > addr, > - base, 0, 1, 0, true, false); > + base, 0, 1, 0, false); > } > } > > @@ -2660,7 +2660,7 @@ static void emit_streamout_output(struct > si_shader_context *ctx, > vdata, num_comps, > so_write_offsets[buf_idx], > ctx->i32_0, > - stream_out->dst_offset * 4, 1, 1, > true, false); > + stream_out->dst_offset * 4, 1, 1, > false); > } > > /** > @@ -3054,7 +3054,7 @@ static void si_copy_tcs_inputs(struct > lp_build_tgsi_context *bld_base) > LLVMValueRef value = lshs_lds_load(bld_base, ctx->ac.i32, > ~0, lds_ptr); > > ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, > buffer_addr, > - buffer_offset, 0, 1, 0, true, > false); > + buffer_offset, 0, 1, 0, false); > } > } > > @@ -3180,7 +3180,7 @@ static void si_write_tess_factors(struct > lp_build_tgsi_context *bld_base, > ac_build_buffer_store_dword(&ctx->ac, buffer, > LLVMConstInt(ctx->i32, > 0x80000000, 0), > 1, ctx->i32_0, tf_base, > - offset, 1, 0, true, false); > + offset, 1, 0, false); > offset += 4; > } > > @@ -3189,12 +3189,12 @@ static void si_write_tess_factors(struct > lp_build_tgsi_context *bld_base, > /* Store the tessellation factors. */ > ac_build_buffer_store_dword(&ctx->ac, buffer, vec0, > MIN2(stride, 4), byteoffset, tf_base, > - offset, 1, 0, true, false); > + offset, 1, 0, false); > offset += 16; > if (vec1) > ac_build_buffer_store_dword(&ctx->ac, buffer, vec1, > stride - 4, byteoffset, > tf_base, > - offset, 1, 0, true, false); > + offset, 1, 0, false); > > /* Store the tess factors into the offchip buffer if TES reads > them. */ > if (shader->key.part.tcs.epilog.tes_reads_tess_factors) { @@ > -3217,7 +3217,7 @@ static void si_write_tess_factors(struct > lp_build_tgsi_context *bld_base, > > ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec, > outer_comps, tf_outer_offset, > - base, 0, 1, 0, true, false); > + base, 0, 1, 0, false); > if (inner_comps) { > param_inner = si_shader_io_get_unique_index_patch( > TGSI_SEMANTIC_TESSINNER, 0); > @@ -3228,7 +3228,7 @@ static void si_write_tess_factors(struct > lp_build_tgsi_context *bld_base, > ac_build_gather_values(&ctx->ac, > inner, inner_comps); > ac_build_buffer_store_dword(&ctx->ac, buf, > inner_vec, > inner_comps, > tf_inner_offset, > - base, 0, 1, 0, true, > false); > + base, 0, 1, 0, false); > } > } > > @@ -3535,7 +3535,7 @@ static void si_llvm_emit_es_epilogue(struct > ac_shader_abi *abi, > ctx->esgs_ring, > out_val, 1, NULL, > soffset, > (4 * param + chan) * 4, > - 1, 1, true, true); > + 1, 1, true); > } > } > > @@ -4247,7 +4247,7 @@ static void si_llvm_emit_vertex(struct ac_shader_abi > *abi, > ctx->gsvs_ring[stream], > out_val, 1, > voffset, soffset, 0, > - 1, 1, true, true); > + 1, 1, true); > } > } > > diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c > b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c > index 5f60d8dc33f..a2e6a47cba3 100644 > --- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c > +++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c > @@ -635,7 +635,7 @@ static void store_emit_buffer(struct si_shader_context > *ctx, > voff, ctx->i32_0, 0, > !!(cache_policy & ac_glc), > !!(cache_policy & ac_slc), > - writeonly_memory, false); > + false); > } > } > > @@ -728,13 +728,13 @@ static void store_emit( > > ac_build_gather_values(&ctx->ac, chans, num_channels), > vindex, ctx->i32_0 /* voffset > */, > num_channels, > - !!(args.cache_policy & > ac_glc), false, > - writeonly_memory); > + !!(args.cache_policy & > ac_glc), > + false); > } else { > args.opcode = ac_image_store; > args.data[0] = ac_build_gather_values(&ctx->ac, chans, 4); > args.dim = ac_image_dim_from_tgsi_target(ctx->screen, > inst->Memory.Texture); > - args.attributes = > ac_get_store_intr_attribs(writeonly_memory); > + args.attributes = AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY; > args.dmask = 0xf; > > emit_data->output[emit_data->chan] = > -- > 2.17.2 > >
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