On Tue, Mar 05, 2019 at 09:40:20AM +0000, Chris Wilson wrote:
> Not all commands support being preempted as they execute, and for those
> make sure we at least check for being preempted before we start so as to
> try and minimise the latency of whomever is more important than
> ourselves.
>
> Cc: Jari Tahvanainen <jari.tahvanai...@intel.com>,
> Cc: Rafael Antognolli <rafael.antogno...@intel.com>
> Cc: Kenneth Graunke <kenn...@whitecape.org>
> ---
> Always double check before you hit send.
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 1 +
> src/mesa/drivers/dri/i965/brw_draw.c | 7 +++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 2729a54e144..ef71c556cca 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -1420,6 +1420,7 @@ enum brw_pixel_shader_coverage_mask_mode {
>
> #define MI_NOOP (CMD_MI | 0)
>
> +#define MI_ARB_CHECK (CMD_MI | 0x5 << 23)
> #define MI_BATCH_BUFFER_END (CMD_MI | 0xA << 23)
>
> #define MI_FLUSH (CMD_MI | (4 << 23))
> diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
> b/src/mesa/drivers/dri/i965/brw_draw.c
> index d07349419cc..a04e334ffc4 100644
> --- a/src/mesa/drivers/dri/i965/brw_draw.c
> +++ b/src/mesa/drivers/dri/i965/brw_draw.c
> @@ -196,6 +196,13 @@ brw_emit_prim(struct brw_context *brw,
> if (verts_per_instance == 0 && !prim->is_indirect && !xfb_obj)
> return;
>
> + /* If this object is not itself preemptible, check before we begin. */
> + if (!brw->object_preemption) {
> + BEGIN_BATCH(1);
> + OUT_BATCH(MI_ARB_CHECK);
> + ADVANCE_BATCH();
> + }
> +
"The command streamer will preempt in the case arbitration is enabled,
there is a pending execution list and this command is currently being
parsed."
If there is a pending execution list, shouldn't we have been preempted
already, since mid-batch preemption is supposed to be enabled?
> /* If we're set to always flush, do it before and after the primitive
> emit.
> * We want to catch both missed flushes that hurt instruction/state cache
> * and missed flushes of the render cache as it heads to other parts of
> --
> 2.20.1
>
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