Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
---
src/intel/compiler/brw_eu.h | 4 ---
src/intel/compiler/brw_eu_emit.c | 36 -------------------------
src/intel/compiler/brw_fs_generator.cpp | 13 +++++++--
src/intel/compiler/brw_fs_nir.cpp | 18 +++++++++++--
4 files changed, 27 insertions(+), 44 deletions(-)
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 2309d3b10d8..ae068964936 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -673,10 +673,6 @@ brw_broadcast(struct brw_codegen *p,
struct brw_reg src,
struct brw_reg idx);
-void
-brw_rounding_mode(struct brw_codegen *p,
- enum brw_rnd_mode mode);
-
void
brw_float_controls_mode(struct brw_codegen *p,
unsigned mode, unsigned mask);
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index f0193712a9f..cda6f3ea70f 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3634,42 +3634,6 @@ brw_WAIT(struct brw_codegen *p)
brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
}
-/**
- * Changes the floating point rounding mode updating the control register
- * field defined at cr0.0[5-6] bits. This function supports the changes to
- * RTNE (00), RU (01), RD (10) and RTZ (11) rounding using bitwise operations.
- * Only RTNE and RTZ rounding are enabled at nir.
- */
-void
-brw_rounding_mode(struct brw_codegen *p,
- enum brw_rnd_mode mode)
-{
- const unsigned bits = mode << BRW_CR0_RND_MODE_SHIFT;
-
- if (bits != BRW_CR0_RND_MODE_MASK) {
- brw_inst *inst = brw_AND(p, brw_cr0_reg(0), brw_cr0_reg(0),
- brw_imm_ud(~BRW_CR0_RND_MODE_MASK));
- brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1);
-
- /* From the Skylake PRM, Volume 7, page 760:
- * "Implementation Restriction on Register Access: When the control
- * register is used as an explicit source and/or destination, hardware
- * does not ensure execution pipeline coherency. Software must set the
- * thread control field to ‘switch’ for an instruction that uses
- * control register as an explicit operand."
- */
- brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH);
- }
-
- if (bits) {
- brw_inst *inst = brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0),
- brw_imm_ud(bits));
- brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1);
- brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH);
- }
-}
-
-/* TODO: Refactor brw_rounding_mode() to use this. */
void
brw_float_controls_mode(struct brw_codegen *p,
unsigned mode, unsigned mask)
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.cpp
index 7ae42a639f8..d92ee063893 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -2423,9 +2423,18 @@ fs_generator::generate_code(const cfg_t *cfg, int
dispatch_width)
brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
break;
- case SHADER_OPCODE_RND_MODE:
+ case SHADER_OPCODE_RND_MODE: {
assert(src[0].file == BRW_IMMEDIATE_VALUE);
- brw_rounding_mode(p, (enum brw_rnd_mode) src[0].d);
+ /*
+ * Changes the floating point rounding mode updating the control
register
+ * field defined at cr0.0[5-6] bits. This function supports the
changes to
+ * RTNE (00), RU (01), RD (10) and RTZ (11) rounding using bitwise
operations.
+ * Only RTNE and RTZ rounding are enabled at nir.
+ */
+ enum brw_rnd_mode mode =
+ (enum brw_rnd_mode) (src[0].d << BRW_CR0_RND_MODE_SHIFT);
+ brw_float_controls_mode(p, mode, BRW_CR0_RND_MODE_MASK);
+ }
break;
case SHADER_OPCODE_FLOAT_CONTROL_MODE:
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index de24a322e68..28f38949f73 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -653,10 +653,15 @@ emit_find_msb_using_lzd(const fs_builder &bld,
}
static brw_rnd_mode
-brw_rnd_mode_from_nir_op (const nir_op op) {
+brw_rnd_mode_from_nir_op (const nir_op op)
+{
switch (op) {
+ case nir_op_f2f64_rtz:
+ case nir_op_f2f32_rtz:
case nir_op_f2f16_rtz:
return BRW_RND_MODE_RTZ;
+ case nir_op_f2f64_rtne:
+ case nir_op_f2f32_rtne:
case nir_op_f2f16_rtne:
return BRW_RND_MODE_RTNE;
default:
@@ -803,6 +808,9 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
nir_alu_instr *instr)
case nir_op_f2f64_rtne:
case nir_op_f2f64_rtz:
+ bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
+ brw_imm_d(brw_rnd_mode_from_nir_op(instr->op)));
+ /* fallthrough */
case nir_op_f2f64:
case nir_op_f2i64:
case nir_op_f2u64:
@@ -994,10 +1002,16 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
nir_alu_instr *instr)
bld.MOV(tmp, op[0]);
op[0] = tmp;
}
- /* Fallthrough */
+ inst = bld.MOV(result, op[0]);
+ inst->saturate = instr->dest.saturate;
+ break;
case nir_op_f2f32_rtne:
case nir_op_f2f32_rtz:
+ bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
+ brw_imm_d(brw_rnd_mode_from_nir_op(instr->op)));
+ /* Fallthrough */
+
case nir_op_f2f32:
case nir_op_f2i32:
case nir_op_f2u32:
--
2.19.1
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