On Fri, Aug 31, 2018 at 04:04:22PM -0500, Jason Ekstrand wrote: > We had the flush/stall after the clear but missed the one that needs to > go before the clear. >
Does this fix the GPU Hang in DiRT 3? > Cc: [email protected] > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107760 > --- > src/intel/vulkan/anv_blorp.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c > index 3dfc8087630..532e8185c0e 100644 > --- a/src/intel/vulkan/anv_blorp.c > +++ b/src/intel/vulkan/anv_blorp.c > @@ -1605,6 +1605,16 @@ anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer, > ISL_AUX_USAGE_NONE, &stencil); > } > > + /* From the Sky Lake PRM Volume 7, "Depth Buffer Clear": > + * > + * "If other rendering operations have preceded this clear, a > + * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit enabled > + * must be issued before the rectangle primitive used for the depth > + * buffer clear operation." > + */ > + cmd_buffer->state.pending_pipe_bits |= > + ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT; > + The PRMs say this pipecontrol is needed only if you're doing a clear with WM_STATE or 3DSTATE_WM. I wonder if we should be doing the pipecontrol that comes after blorp_hiz_clear_depth_stencil() in the case of stencil-only HIZ clears as well? If that doesn't fix it, I think it'd be good to comment that we've observed this pipecontrol be necessary for 3DSTATE_WM_HZ_OP. > blorp_hiz_clear_depth_stencil(&batch, &depth, &stencil, > level, base_layer, layer_count, > area.offset.x, area.offset.y, > -- > 2.17.1 > > _______________________________________________ > mesa-dev mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
