On Wednesday, August 29, 2018 1:12:28 PM PDT Ian Romanick wrote: > From: Ian Romanick <[email protected]> > > Page 190 of "Volume 7: 3D Media GPGPU Engine (Haswell)" says the valid > range of the offset is [0, 0FFFFFFFh]. > > Signed-off-by: Ian Romanick <[email protected]> > Cc: [email protected] > Cc: Kenneth Graunke <[email protected]> > --- > src/intel/compiler/brw_vec4_tes.cpp | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/src/intel/compiler/brw_vec4_tes.cpp > b/src/intel/compiler/brw_vec4_tes.cpp > index 35aff0f4b78..cf1bff42aa9 100644 > --- a/src/intel/compiler/brw_vec4_tes.cpp > +++ b/src/intel/compiler/brw_vec4_tes.cpp > @@ -185,9 +185,19 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr > *instr) > first_component /= 2; > > if (indirect_offset.file != BAD_FILE) { > + src_reg clamped_indirect_offset = src_reg(this, > glsl_type::uvec4_type); > + > + /* Page 190 of "Volume 7: 3D Media GPGPU Engine (Haswell)" says the > + * valid range of the offset is [0, 0FFFFFFFh]. > + */ > + emit_minmax(BRW_CONDITIONAL_L, > + dst_reg(clamped_indirect_offset), > + retype(indirect_offset, BRW_REGISTER_TYPE_UD), > + brw_imm_ud(0x0fffffffu)); > + > header = src_reg(this, glsl_type::uvec4_type); > emit(TES_OPCODE_ADD_INDIRECT_URB_OFFSET, dst_reg(header), > - input_read_header, indirect_offset); > + input_read_header, clamped_indirect_offset); > } else { > /* Arbitrarily only push up to 24 vec4 slots worth of data, > * which is 12 registers (since each holds 2 vec4 slots). >
Both patches are: Reviewed-by: Kenneth Graunke <[email protected]>
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