---
src/gallium/auxiliary/tgsi/tgsi_info.c | 4 +++
src/gallium/docs/source/tgsi.rst | 49 ++++++++++++++++++++++++++++
src/gallium/include/pipe/p_shader_tokens.h | 7 +++-
3 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c
b/src/gallium/auxiliary/tgsi/tgsi_info.c
index a6cd194..2c59060 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -200,6 +200,10 @@ static const struct tgsi_opcode_info
opcode_info[TGSI_OPCODE_LAST] =
{ 1, 1, 0, 0, 0, 0, COMP, "IABS", TGSI_OPCODE_IABS },
{ 1, 1, 0, 0, 0, 0, COMP, "ISSG", TGSI_OPCODE_ISSG },
{ 1, 2, 0, 0, 0, 0, OTHR, "STORE", TGSI_OPCODE_STORE },
+ { 1, 0, 0, 0, 0, 0, OTHR, "MFENCE", TGSI_OPCODE_MFENCE },
+ { 1, 0, 0, 0, 0, 0, OTHR, "LFENCE", TGSI_OPCODE_LFENCE },
+ { 1, 0, 0, 0, 0, 0, OTHR, "SFENCE", TGSI_OPCODE_SFENCE },
+ { 0, 0, 0, 0, 0, 0, OTHR, "BARRIER", TGSI_OPCODE_BARRIER }
};
const struct tgsi_opcode_info *
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index a87f774..141ccef 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -1487,6 +1487,55 @@ instructions. If in doubt double check Direct3D
documentation.
not a render target, the result is 0.
+.. _threadsyncopcodes:
+
+Inter-thread synchronization opcodes
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+These opcodes are intended for communication between threads running
+within the same compute grid, for this reason they're only valid in
+compute programs.
+
+.. opcode:: MFENCE - Memory fence
+
+ Syntax: ``MFENCE resource``
+
+ Example: ``MFENCE RES[0]``
+
+ This opcode forces strong ordering between any memory access
+ operations that affect the specified resource. This means that
+ previous loads and stores (and only those) will be performed and
+ visible to other threads before the program execution continues.
+
+
+.. opcode:: LFENCE - Load memory fence
+
+ Syntax: ``LFENCE resource``
+
+ Example: ``LFENCE RES[0]``
+
+ Similar to MFENCE, but it only affects the ordering of memory loads.
+
+
+.. opcode:: SFENCE - Store memory fence
+
+ Syntax: ``SFENCE resource``
+
+ Example: ``SFENCE RES[0]``
+
+ Similar to MFENCE, but it only affects the ordering of memory stores.
+
+
+.. opcode:: BARRIER - Thread group barrier
+
+ ``BARRIER``
+
+ This opcode suspends the execution of the current thread until all
+ the remaining threads in the working group reach the same point of
+ the program. Results are unspecified if any of the remaining
+ threads terminates or never reaches an executed BARRIER instruction.
+
+
Explanation of symbols used
------------------------------
diff --git a/src/gallium/include/pipe/p_shader_tokens.h
b/src/gallium/include/pipe/p_shader_tokens.h
index d36be0a..772d716 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -407,7 +407,12 @@ struct tgsi_property_data {
#define TGSI_OPCODE_STORE 161
-#define TGSI_OPCODE_LAST 162
+#define TGSI_OPCODE_MFENCE 162
+#define TGSI_OPCODE_LFENCE 163
+#define TGSI_OPCODE_SFENCE 164
+#define TGSI_OPCODE_BARRIER 165
+
+#define TGSI_OPCODE_LAST 166
#define TGSI_SAT_NONE 0 /* do not saturate */
#define TGSI_SAT_ZERO_ONE 1 /* clamp to [0,1] */
--
1.7.9.2
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