Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
for the series.
On Mon, Apr 23, 2018 at 2:43 AM, Dave Airlie <airl...@gmail.com> wrote:
> From: Dave Airlie <airl...@redhat.com>
>
> This refactors the code out to share it between radv and radeonsi.
> ---
> src/amd/common/ac_gpu_info.c | 113
> ++++++++++++++++++++++++++++++++
> src/amd/common/ac_gpu_info.h | 4 ++
> src/amd/vulkan/si_cmd_buffer.c | 108 ++----------------------------
> src/gallium/drivers/radeonsi/si_state.c | 111 ++-----------------------------
> 4 files changed, 130 insertions(+), 206 deletions(-)
>
> diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
> index 47a87650a6d..031fd183b6f 100644
> --- a/src/amd/common/ac_gpu_info.c
> +++ b/src/amd/common/ac_gpu_info.c
> @@ -647,3 +647,116 @@ ac_get_raster_config(struct radeon_info *info,
> *raster_config_p = raster_config;
> *raster_config_1_p = raster_config_1;
> }
> +
> +void
> +ac_get_harvested_configs(struct radeon_info *info,
> + unsigned raster_config,
> + unsigned *cik_raster_config_1_p,
> + unsigned *raster_config_se)
> +{
> + unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
> + unsigned num_se = MAX2(info->max_se, 1);
> + unsigned rb_mask = info->enabled_rb_mask;
> + unsigned num_rb = MIN2(info->num_render_backends, 16);
> + unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
> + unsigned rb_per_se = num_rb / num_se;
> + unsigned se_mask[4];
> + unsigned se;
> +
> + se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
> + se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
> + se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
> + se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
> +
> + assert(num_se == 1 || num_se == 2 || num_se == 4);
> + assert(sh_per_se == 1 || sh_per_se == 2);
> + assert(rb_per_pkr == 1 || rb_per_pkr == 2);
> +
> +
> + if (info->chip_class >= CIK) {
> + unsigned raster_config_1 = *cik_raster_config_1_p;
> + if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
> + (!se_mask[2] && !se_mask[3]))) {
> + raster_config_1 &= C_028354_SE_PAIR_MAP;
> +
> + if (!se_mask[0] && !se_mask[1]) {
> + raster_config_1 |=
> +
> S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
> + } else {
> + raster_config_1 |=
> +
> S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
> + }
> + *cik_raster_config_1_p = raster_config_1;
> + }
> + }
> +
> + for (se = 0; se < num_se; se++) {
> + unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se *
> rb_per_se);
> + unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
> + int idx = (se / 2) * 2;
> +
> + raster_config_se[se] = raster_config;
> + if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
> + raster_config_se[se] &= C_028350_SE_MAP;
> +
> + if (!se_mask[idx]) {
> + raster_config_se[se] |=
> +
> S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
> + } else {
> + raster_config_se[se] |=
> +
> S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
> + }
> + }
> +
> + pkr0_mask &= rb_mask;
> + pkr1_mask &= rb_mask;
> + if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
> + raster_config_se[se] &= C_028350_PKR_MAP;
> +
> + if (!pkr0_mask) {
> + raster_config_se[se] |=
> +
> S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
> + } else {
> + raster_config_se[se] |=
> +
> S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
> + }
> + }
> +
> + if (rb_per_se >= 2) {
> + unsigned rb0_mask = 1 << (se * rb_per_se);
> + unsigned rb1_mask = rb0_mask << 1;
> +
> + rb0_mask &= rb_mask;
> + rb1_mask &= rb_mask;
> + if (!rb0_mask || !rb1_mask) {
> + raster_config_se[se] &= C_028350_RB_MAP_PKR0;
> +
> + if (!rb0_mask) {
> + raster_config_se[se] |=
> +
> S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
> + } else {
> + raster_config_se[se] |=
> +
> S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
> + }
> + }
> +
> + if (rb_per_se > 2) {
> + rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
> + rb1_mask = rb0_mask << 1;
> + rb0_mask &= rb_mask;
> + rb1_mask &= rb_mask;
> + if (!rb0_mask || !rb1_mask) {
> + raster_config_se[se] &=
> C_028350_RB_MAP_PKR1;
> +
> + if (!rb0_mask) {
> + raster_config_se[se] |=
> +
> S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
> + } else {
> + raster_config_se[se] |=
> +
> S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
> + }
> + }
> + }
> + }
> + }
> +}
> diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
> index de566c62fa9..7af6fbfca97 100644
> --- a/src/amd/common/ac_gpu_info.h
> +++ b/src/amd/common/ac_gpu_info.h
> @@ -134,6 +134,10 @@ int ac_get_gs_table_depth(enum chip_class chip_class,
> enum radeon_family family)
> void ac_get_raster_config(struct radeon_info *info,
> uint32_t *raster_config_p,
> uint32_t *raster_config_1_p);
> +void ac_get_harvested_configs(struct radeon_info *info,
> + unsigned raster_config,
> + unsigned *cik_raster_config_1_p,
> + unsigned *raster_config_se);
>
> static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
> {
> diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
> index 2140368c80d..4c3a888f3cf 100644
> --- a/src/amd/vulkan/si_cmd_buffer.c
> +++ b/src/amd/vulkan/si_cmd_buffer.c
> @@ -41,97 +41,16 @@ si_write_harvested_raster_configs(struct
> radv_physical_device *physical_device,
> unsigned raster_config,
> unsigned raster_config_1)
> {
> - unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
> unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
> - unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
> - unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends,
> 16);
> - unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
> - unsigned rb_per_se = num_rb / num_se;
> - unsigned se_mask[4];
> + unsigned raster_config_se[4];
> unsigned se;
>
> - se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
> - se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
> - se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
> - se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
> -
> - assert(num_se == 1 || num_se == 2 || num_se == 4);
> - assert(sh_per_se == 1 || sh_per_se == 2);
> - assert(rb_per_pkr == 1 || rb_per_pkr == 2);
> -
> - /* XXX: I can't figure out what the *_XSEL and *_YSEL
> - * fields are for, so I'm leaving them as their default
> - * values. */
> + ac_get_harvested_configs(&physical_device->rad_info,
> + raster_config,
> + &raster_config_1,
> + raster_config_se);
>
> for (se = 0; se < num_se; se++) {
> - unsigned raster_config_se = raster_config;
> - unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se *
> rb_per_se);
> - unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
> - int idx = (se / 2) * 2;
> -
> - if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
> - raster_config_se &= C_028350_SE_MAP;
> -
> - if (!se_mask[idx]) {
> - raster_config_se |=
> -
> S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
> - } else {
> - raster_config_se |=
> -
> S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
> - }
> - }
> -
> - pkr0_mask &= rb_mask;
> - pkr1_mask &= rb_mask;
> - if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
> - raster_config_se &= C_028350_PKR_MAP;
> -
> - if (!pkr0_mask) {
> - raster_config_se |=
> -
> S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
> - } else {
> - raster_config_se |=
> -
> S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
> - }
> - }
> -
> - if (rb_per_se >= 2) {
> - unsigned rb0_mask = 1 << (se * rb_per_se);
> - unsigned rb1_mask = rb0_mask << 1;
> -
> - rb0_mask &= rb_mask;
> - rb1_mask &= rb_mask;
> - if (!rb0_mask || !rb1_mask) {
> - raster_config_se &= C_028350_RB_MAP_PKR0;
> -
> - if (!rb0_mask) {
> - raster_config_se |=
> -
> S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
> - } else {
> - raster_config_se |=
> -
> S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
> - }
> - }
> -
> - if (rb_per_se > 2) {
> - rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
> - rb1_mask = rb0_mask << 1;
> - rb0_mask &= rb_mask;
> - rb1_mask &= rb_mask;
> - if (!rb0_mask || !rb1_mask) {
> - raster_config_se &=
> C_028350_RB_MAP_PKR1;
> -
> - if (!rb0_mask) {
> - raster_config_se |=
> -
> S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
> - } else {
> - raster_config_se |=
> -
> S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
> - }
> - }
> - }
> - }
> -
> /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
> if (physical_device->rad_info.chip_class < CIK)
> radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
> @@ -142,7 +61,7 @@ si_write_harvested_raster_configs(struct
> radv_physical_device *physical_device,
> radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
> S_030800_SE_INDEX(se) |
> S_030800_SH_BROADCAST_WRITES(1) |
>
> S_030800_INSTANCE_BROADCAST_WRITES(1));
> - radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
> raster_config_se);
> + radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
> raster_config_se[se]);
> }
>
> /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
> @@ -156,21 +75,8 @@ si_write_harvested_raster_configs(struct
> radv_physical_device *physical_device,
> S_030800_SE_BROADCAST_WRITES(1) |
> S_030800_SH_BROADCAST_WRITES(1) |
> S_030800_INSTANCE_BROADCAST_WRITES(1));
>
> - if (physical_device->rad_info.chip_class >= CIK) {
> - if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
> - (!se_mask[2] && !se_mask[3]))) {
> - raster_config_1 &= C_028354_SE_PAIR_MAP;
> -
> - if (!se_mask[0] && !se_mask[1]) {
> - raster_config_1 |=
> -
> S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
> - } else {
> - raster_config_1 |=
> -
> S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
> - }
> - }
> + if (physical_device->rad_info.chip_class >= CIK)
> radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
> raster_config_1);
> - }
> }
>
> static void
> diff --git a/src/gallium/drivers/radeonsi/si_state.c
> b/src/gallium/drivers/radeonsi/si_state.c
> index 71e769ed80e..617b293e165 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -4621,121 +4621,22 @@ si_write_harvested_raster_configs(struct si_context
> *sctx,
> unsigned raster_config,
> unsigned raster_config_1)
> {
> - unsigned sh_per_se = MAX2(sctx->screen->info.max_sh_per_se, 1);
> unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
> - unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
> - unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
> - unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
> - unsigned rb_per_se = num_rb / num_se;
> - unsigned se_mask[4];
> + unsigned raster_config_se[4];
> unsigned se;
>
> - se_mask[0] = ((1 << rb_per_se) - 1);
> - se_mask[1] = (se_mask[0] << rb_per_se);
> - se_mask[2] = (se_mask[1] << rb_per_se);
> - se_mask[3] = (se_mask[2] << rb_per_se);
> -
> - se_mask[0] &= rb_mask;
> - se_mask[1] &= rb_mask;
> - se_mask[2] &= rb_mask;
> - se_mask[3] &= rb_mask;
> -
> - assert(num_se == 1 || num_se == 2 || num_se == 4);
> - assert(sh_per_se == 1 || sh_per_se == 2);
> - assert(rb_per_pkr == 1 || rb_per_pkr == 2);
> -
> - /* XXX: I can't figure out what the *_XSEL and *_YSEL
> - * fields are for, so I'm leaving them as their default
> - * values. */
> + ac_get_harvested_configs(&sctx->screen->info,
> + raster_config,
> + &raster_config_1,
> + raster_config_se);
>
> for (se = 0; se < num_se; se++) {
> - unsigned raster_config_se = raster_config;
> - unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se *
> rb_per_se);
> - unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
> - int idx = (se / 2) * 2;
> -
> - if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
> - raster_config_se &= C_028350_SE_MAP;
> -
> - if (!se_mask[idx]) {
> - raster_config_se |=
> -
> S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
> - } else {
> - raster_config_se |=
> -
> S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
> - }
> - }
> -
> - pkr0_mask &= rb_mask;
> - pkr1_mask &= rb_mask;
> - if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
> - raster_config_se &= C_028350_PKR_MAP;
> -
> - if (!pkr0_mask) {
> - raster_config_se |=
> -
> S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
> - } else {
> - raster_config_se |=
> -
> S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
> - }
> - }
> -
> - if (rb_per_se >= 2) {
> - unsigned rb0_mask = 1 << (se * rb_per_se);
> - unsigned rb1_mask = rb0_mask << 1;
> -
> - rb0_mask &= rb_mask;
> - rb1_mask &= rb_mask;
> - if (!rb0_mask || !rb1_mask) {
> - raster_config_se &= C_028350_RB_MAP_PKR0;
> -
> - if (!rb0_mask) {
> - raster_config_se |=
> -
> S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
> - } else {
> - raster_config_se |=
> -
> S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
> - }
> - }
> -
> - if (rb_per_se > 2) {
> - rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
> - rb1_mask = rb0_mask << 1;
> - rb0_mask &= rb_mask;
> - rb1_mask &= rb_mask;
> - if (!rb0_mask || !rb1_mask) {
> - raster_config_se &=
> C_028350_RB_MAP_PKR1;
> -
> - if (!rb0_mask) {
> - raster_config_se |=
> -
> S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
> - } else {
> - raster_config_se |=
> -
> S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
> - }
> - }
> - }
> - }
> -
> si_set_grbm_gfx_index_se(sctx, pm4, se);
> - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
> raster_config_se);
> + si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
> raster_config_se[se]);
> }
> si_set_grbm_gfx_index(sctx, pm4, ~0);
>
> if (sctx->chip_class >= CIK) {
> - if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
> - (!se_mask[2] && !se_mask[3]))) {
> - raster_config_1 &= C_028354_SE_PAIR_MAP;
> -
> - if (!se_mask[0] && !se_mask[1]) {
> - raster_config_1 |=
> -
> S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
> - } else {
> - raster_config_1 |=
> -
> S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
> - }
> - }
> -
> si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
> raster_config_1);
> }
> }
> --
> 2.14.3
>
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