This is imported from RadeonSI/ADMVLK. That might or might not
improve performance. Anyway, it's still disabled by default.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
src/amd/vulkan/radv_pipeline.c | 56 +++++++++++++++++++++++++++++++++++++++++-
1 file changed, 55 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index dd5baec117..6c0d552c81 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2134,6 +2134,59 @@ radv_compute_bin_size(struct radv_pipeline *pipeline,
const VkGraphicsPipelineCr
return extent;
}
+static bool
+radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo)
+{
+ assert(pCreateInfo);
+ return pCreateInfo->depthTestEnable &&
+ pCreateInfo->depthWriteEnable &&
+ pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
+}
+
+static bool
+radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo)
+{
+ assert(pCreateInfo);
+ return pCreateInfo->stencilTestEnable &&
+ (pCreateInfo->front.failOp != VK_STENCIL_OP_KEEP ||
+ pCreateInfo->front.passOp != VK_STENCIL_OP_KEEP ||
+ pCreateInfo->front.depthFailOp != VK_STENCIL_OP_KEEP ||
+ pCreateInfo->back.failOp != VK_STENCIL_OP_KEEP ||
+ pCreateInfo->back.passOp != VK_STENCIL_OP_KEEP ||
+ pCreateInfo->back.depthFailOp != VK_STENCIL_OP_KEEP);
+}
+
+static bool
+radv_should_enable_pbb(struct radv_pipeline *pipeline,
+ const VkGraphicsPipelineCreateInfo *pCreateInfo)
+{
+ RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
+ struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
+ struct radv_shader_variant *ps =
pipeline->shaders[MESA_SHADER_FRAGMENT];
+
+ if (!pipeline->device->pbb_allowed)
+ return false;
+
+ /* Whether we can disable binning state based on the pixel shader, MSAA
+ * states and depth/stencil writes.
+ */
+ bool ps_can_kill = ps->info.fs.can_discard ||
+ ps->info.info.ps.writes_sample_mask ||
+ pCreateInfo->pMultisampleState;
+ bool ps_can_reject_z_trivially = !ps->info.info.ps.writes_z;
+ bool ds_write_enabled =
+ pCreateInfo->pDepthStencilState &&
+ subpass->depth_stencil_attachment.attachment !=
VK_ATTACHMENT_UNUSED &&
+ (radv_is_depth_write_enabled(pCreateInfo->pDepthStencilState) ||
+
radv_is_stencil_write_enabled(pCreateInfo->pDepthStencilState));
+
+ /* Disable binning state if PS can kill trivially with DB writes. */
+ if (ps_can_kill && ps_can_reject_z_trivially && ds_write_enabled)
+ return false;
+
+ return true;
+}
+
static void
radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
struct radv_pipeline *pipeline,
@@ -2168,7 +2221,8 @@ radv_pipeline_generate_binning_state(struct
radeon_winsys_cs *cs,
unreachable("unhandled family while determining binning
state.");
}
- if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height)
{
+ if (radv_should_enable_pbb(pipeline, pCreateInfo) &&
+ bin_size.width && bin_size.height) {
pa_sc_binner_cntl_0 =
S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
S_028C44_BIN_SIZE_X(bin_size.width == 16) |
--
2.16.2
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