Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_defines.h | 8 ++++++-
src/mesa/drivers/dri/i965/brw_misc_state.c | 33 +++++++++++++++++++++++++++
src/mesa/drivers/dri/i965/brw_state.h | 1 +
src/mesa/drivers/dri/i965/brw_state_upload.c | 2 ++
src/mesa/drivers/dri/i965/genX_state_upload.c | 3 +++
src/mesa/drivers/dri/i965/intel_extensions.c | 3 +++
7 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 177273c3645..ded1f1085c3 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -216,6 +216,7 @@ enum brw_state_id {
BRW_STATE_CONSERVATIVE_RASTERIZATION,
BRW_STATE_DRAW_CALL,
BRW_STATE_AUX,
+ BRW_STATE_BLACKHOLE_RENDER,
BRW_NUM_STATE_BITS
};
@@ -307,6 +308,7 @@ enum brw_state_id {
#define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull <<
BRW_STATE_CONSERVATIVE_RASTERIZATION)
#define BRW_NEW_DRAW_CALL (1ull << BRW_STATE_DRAW_CALL)
#define BRW_NEW_AUX_STATE (1ull << BRW_STATE_AUX)
+#define BRW_NEW_BLACKHOLE_RENDER (1ull << BRW_STATE_BLACKHOLE_RENDER)
struct brw_state_flags {
/** State update flags signalled by mesa internals */
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 8bf6f68b67c..c8a597c8ad0 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1650,11 +1650,17 @@ enum brw_pixel_shader_coverage_mask_mode {
#define GEN10_CACHE_MODE_SS 0x0e420
#define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
-#define INSTPM 0x20c0
+#define INSTPM 0x20c0 /* Gen6-8 */
# define INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 6)
+# define INSTPM_GLOBAL_DEBUG_ENABLE (1 << 4)
+# define INSTPM_MEDIA_INSTRUCTION_DISABLE (1 << 3)
+# define INSTPM_3D_RENDERER_INSTRUCTION_DISABLE (1 << 2)
+# define INSTPM_3D_STATE_INSTRUCTION_DISABLE (1 << 1)
#define CS_DEBUG_MODE2 0x20d8 /* Gen9+ */
# define CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 4)
+# define CSDBG2_MEDIA_INSTRUCTION_DISABLE (1 << 1)
+# define CSDBG2_3D_RENDERER_INSTRUCTION_DISABLE (1 << 0)
#define SLICE_COMMON_ECO_CHICKEN1 0x731c /* Gen9+ */
# define GLK_SCEC_BARRIER_MODE_GPGPU (0 << 7)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 29d74876c27..583578d2a2f 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -766,3 +766,36 @@ brw_upload_state_base_address(struct brw_context *brw)
brw->ctx.NewDriverState |= BRW_NEW_STATE_BASE_ADDRESS;
brw->batch.state_base_address_emitted = true;
}
+
+static void
+brw_emit_blackhole_render(struct brw_context *brw)
+{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ struct gl_context *ctx = &brw->ctx;
+ uint32_t reg_offset = devinfo->gen >= 9 ? CS_DEBUG_MODE2 : INSTPM;
+ uint32_t reg_mask = devinfo->gen >= 9 ?
+ REG_MASK(CSDBG2_3D_RENDERER_INSTRUCTION_DISABLE |
+ CSDBG2_MEDIA_INSTRUCTION_DISABLE) :
+ REG_MASK(INSTPM_3D_RENDERER_INSTRUCTION_DISABLE |
+ INSTPM_MEDIA_INSTRUCTION_DISABLE);
+ uint32_t reg_value = 0;
+
+ if (ctx->IntelBlackholeRender) {
+ reg_value = devinfo->gen >= 9 ?
+ (CSDBG2_3D_RENDERER_INSTRUCTION_DISABLE |
+ CSDBG2_MEDIA_INSTRUCTION_DISABLE) :
+ (INSTPM_3D_RENDERER_INSTRUCTION_DISABLE |
+ INSTPM_MEDIA_INSTRUCTION_DISABLE);
+ }
+
+ brw_load_register_imm32(brw, reg_offset, reg_mask | reg_value);
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_LRI_WRITE_IMMEDIATE);
+}
+
+const struct brw_tracked_state brw_blackhole_render = {
+ .dirty = {
+ .mesa = 0,
+ .brw = BRW_NEW_BLACKHOLE_RENDER,
+ },
+ .emit = brw_emit_blackhole_render,
+};
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 9acb6257401..e5e60985517 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -95,6 +95,7 @@ extern const struct brw_tracked_state
gen7_push_constant_space;
extern const struct brw_tracked_state gen7_urb;
extern const struct brw_tracked_state gen8_pma_fix;
extern const struct brw_tracked_state brw_cs_work_groups_surface;
+extern const struct brw_tracked_state brw_blackhole_render;
static inline bool
brw_state_dirty(const struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index d8273aa5734..70a8526e952 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -234,6 +234,7 @@ void brw_init_state( struct brw_context *brw )
ctx->DriverFlags.NewImageUnits = BRW_NEW_IMAGE_UNITS;
ctx->DriverFlags.NewDefaultTessLevels = BRW_NEW_DEFAULT_TESS_LEVELS;
ctx->DriverFlags.NewIntelConservativeRasterization =
BRW_NEW_CONSERVATIVE_RASTERIZATION;
+ ctx->DriverFlags.NewIntelBlackholeRender = BRW_NEW_BLACKHOLE_RENDER;
}
@@ -369,6 +370,7 @@ static struct dirty_bit_map brw_bits[] = {
DEFINE_BIT(BRW_NEW_CONSERVATIVE_RASTERIZATION),
DEFINE_BIT(BRW_NEW_DRAW_CALL),
DEFINE_BIT(BRW_NEW_AUX_STATE),
+ DEFINE_BIT(BRW_NEW_BLACKHOLE_RENDER),
{0, 0, 0}
};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index a69a496f1db..b4ec30434b6 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -5616,6 +5616,7 @@ genX(init_atoms)(struct brw_context *brw)
#if GEN_IS_HASWELL
&genX(cut_index),
+ &brw_blackhole_render,
#endif
};
#elif GEN_GEN >= 8
@@ -5709,6 +5710,7 @@ genX(init_atoms)(struct brw_context *brw)
&genX(cut_index),
&gen8_pma_fix,
+ &brw_blackhole_render,
};
#endif
@@ -5728,6 +5730,7 @@ genX(init_atoms)(struct brw_context *brw)
&brw_cs_work_groups_surface,
&genX(cs_samplers),
&genX(cs_state),
+ &brw_blackhole_render,
};
STATIC_ASSERT(ARRAY_SIZE(compute_atoms) <= ARRAY_SIZE(brw->compute_atoms));
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 73a6c73f537..12d22e12eee 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -279,6 +279,9 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.OES_copy_image = true;
}
+ if (devinfo->gen >= 8 || devinfo->is_haswell)
+ ctx->Extensions.INTEL_blackhole_render = true;
+
if (devinfo->gen >= 8) {
ctx->Extensions.ARB_gpu_shader_int64 = devinfo->has_64bit_types;
/* requires ARB_gpu_shader_int64 */
--
2.16.2
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
