Signed-off-by: Anuj Phogat <[email protected]>
---
src/intel/vulkan/genX_pipeline.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 85391c93ca..290d78e608 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1124,6 +1124,9 @@ emit_3dstate_vs(struct anv_pipeline *pipeline)
pipeline->shaders[MESA_SHADER_VERTEX];
assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX));
+#if GEN_GEN >= 11
+ assert(vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
+#endif
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
vs.Enable = true;
@@ -1253,10 +1256,14 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline,
tes_prog_data->base.base.dispatch_grf_start_reg;
#if GEN_GEN >= 8
+#if GEN_GEN < 11
ds.DispatchMode =
tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8 ?
DISPATCH_MODE_SIMD8_SINGLE_PATCH :
DISPATCH_MODE_SIMD4X2;
+#else
+ ds.DispatchMode = DISPATCH_MODE_SIMD8_SINGLE_PATCH;
+#endif
ds.UserClipDistanceClipTestEnableBitmask =
tes_prog_data->base.clip_distance_mask;
--
2.13.6
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