On 12/12/17 20:56, Nicolai Hähnle wrote:
What about reads_pervertex_outputs?
There is no load output support in this series at all, I was hoping to
do that as a follow up series.
Cheers,
Nicolai
On 11.12.2017 03:43, Timothy Arceri wrote:
---
src/gallium/drivers/radeonsi/si_shader_nir.c | 29
++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 4138e04dcb5..d2760b03bca 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -76,32 +76,39 @@ static void scan_instruction(struct
tgsi_shader_info *info,
} else if (instr->type == nir_instr_type_intrinsic) {
nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
switch (intr->intrinsic) {
case nir_intrinsic_load_front_face:
info->uses_frontface = 1;
break;
case nir_intrinsic_load_instance_id:
info->uses_instanceid = 1;
break;
+ case nir_intrinsic_load_invocation_id:
+ info->uses_invocationid = true;
+ break;
case nir_intrinsic_load_vertex_id:
info->uses_vertexid = 1;
break;
case nir_intrinsic_load_vertex_id_zero_base:
info->uses_vertexid_nobase = 1;
break;
case nir_intrinsic_load_base_vertex:
info->uses_basevertex = 1;
break;
case nir_intrinsic_load_primitive_id:
info->uses_primid = 1;
break;
+ case nir_intrinsic_load_tess_level_inner:
+ case nir_intrinsic_load_tess_level_outer:
+ info->reads_tess_factors = true;
+ break;
case nir_intrinsic_image_store:
case nir_intrinsic_image_atomic_add:
case nir_intrinsic_image_atomic_min:
case nir_intrinsic_image_atomic_max:
case nir_intrinsic_image_atomic_and:
case nir_intrinsic_image_atomic_or:
case nir_intrinsic_image_atomic_xor:
case nir_intrinsic_image_atomic_exchange:
case nir_intrinsic_image_atomic_comp_swap:
case nir_intrinsic_store_ssbo:
@@ -130,20 +137,42 @@ void si_nir_scan_shader(const struct nir_shader
*nir,
unsigned i;
assert(nir->info.stage == MESA_SHADER_VERTEX ||
nir->info.stage == MESA_SHADER_GEOMETRY ||
nir->info.stage == MESA_SHADER_FRAGMENT);
info->processor = pipe_shader_type_from_mesa(nir->info.stage);
info->num_tokens = 2; /* indicate that the shader is non-empty */
info->num_instructions = 2;
+ if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
+ info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
+ nir->info.tess.tcs_vertices_out;
+ }
+
+ if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
+ if (nir->info.tess.primitive_mode == GL_ISOLINES)
+ info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = GL_LINES;
+ else
+ info->properties[TGSI_PROPERTY_TES_PRIM_MODE] =
nir->info.tess.primitive_mode;
+
+ STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 ==
PIPE_TESS_SPACING_EQUAL);
+ STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
+ PIPE_TESS_SPACING_FRACTIONAL_ODD);
+ STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
+ PIPE_TESS_SPACING_FRACTIONAL_EVEN);
+
+ info->properties[TGSI_PROPERTY_TES_SPACING] =
(nir->info.tess.spacing + 1) % 3;
+ info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] =
!nir->info.tess.ccw;
+ info->properties[TGSI_PROPERTY_TES_POINT_MODE] =
nir->info.tess.point_mode;
+ }
+
if (nir->info.stage == MESA_SHADER_GEOMETRY) {
info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] =
nir->info.gs.input_primitive;
info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] =
nir->info.gs.output_primitive;
info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] =
nir->info.gs.vertices_out;
info->properties[TGSI_PROPERTY_GS_INVOCATIONS] =
nir->info.gs.invocations;
}
i = 0;
uint64_t processed_inputs = 0;
unsigned num_inputs = 0;
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