On Fri, Sep 29, 2017 at 5:20 PM, Scott D Phillips
<scott.d.phill...@intel.com> wrote:
> Matt Turner <matts...@gmail.com> writes:
>
>> Align1 mode offers some nice features over align16, like access to more
>> data types and the ability to use a 16-bit immediate. This patch does
>> not start using any new features. It just emits ternary instructions in
>> align1 mode.
>> ---
>> src/intel/compiler/brw_fs_generator.cpp | 12 ++++++++----
>> 1 file changed, 8 insertions(+), 4 deletions(-)
>>
>> diff --git a/src/intel/compiler/brw_fs_generator.cpp
>> b/src/intel/compiler/brw_fs_generator.cpp
>> index afaec5c949..03ee26ccd4 100644
>> --- a/src/intel/compiler/brw_fs_generator.cpp
>> +++ b/src/intel/compiler/brw_fs_generator.cpp
>> @@ -1728,14 +1728,16 @@ fs_generator::generate_code(const cfg_t *cfg, int
>> dispatch_width)
>>
>> case BRW_OPCODE_MAD:
>> assert(devinfo->gen >= 6);
>> - brw_set_default_access_mode(p, BRW_ALIGN_16);
>> + if (devinfo->gen < 10)
>> + brw_set_default_access_mode(p, BRW_ALIGN_16);
>
> Not setting anything gets BRW_ALIGN_1 because its enum value is 0. Maybe
> add a comment for that if you want.
Actually, it's set at the top of the loop:
brw_set_default_access_mode(p, BRW_ALIGN_1);
along with some other defaults. This is done, because align1 mode
matches well with the scalar mode that the fragment shader runs in
(and on Gen8+ all other stages too).
>> brw_MAD(p, dst, src[0], src[1], src[2]);
>> break;
>>
>> case BRW_OPCODE_LRP:
>> assert(devinfo->gen >= 6);
>> brw_set_default_access_mode(p, BRW_ALIGN_16);
>> - brw_LRP(p, dst, src[0], src[1], src[2]);
>> + if (devinfo->gen < 10)
>> + brw_LRP(p, dst, src[0], src[1], src[2]);
>
> Copy paste error
Whoops. Thanks. Fixed locally.
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
