This reverts commit bebc91f0f3a1f2d19d36a7f1a4f7c992ace064e9.
Fixes the following Piglit regressions on gen7:
spec/ARB_depth_buffer_float/fbo-clear-formats
spec/ARB_depth_texture/fbo-clear-formats
spec/EXT_packed_depth_stencil/fbo-clear-formats
I mistakenly thought that depth_rb->Width and depth_irb->mt->region->width
were identical. But of course they're not when there are multiple images
in the miptree.
To fix the compile, the commit below is also reverted:
commit 254b24f19511014cdf4741b73d69349ac9e931a2.
i965: Fix compiler warnings from hiz changes
CC: Eric Anholt <e...@anholt.net>
CC: Kenneth Graunke <kenn...@whitecape.org>
Signed-off-by: Chad Versace <chad.vers...@linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 10 ++++++----
src/mesa/drivers/dri/i965/gen7_misc_state.c | 8 ++++----
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index f9652df..1c0c52b 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -330,6 +330,8 @@ static void emit_depthbuffer(struct brw_context *brw)
* Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
* [DevGT+]: This field must be set to TRUE.
*/
+ struct intel_region *region = stencil_mt->region;
+
assert(intel->has_separate_stencil);
BEGIN_BATCH(len);
@@ -341,8 +343,8 @@ static void emit_depthbuffer(struct brw_context *brw)
(1 << 27) | /* tiled surface */
(BRW_SURFACE_2D << 29));
OUT_BATCH(0);
- OUT_BATCH(((stencil_irb->Base.Width - 1) << 6) |
- (stencil_irb->Base.Height - 1) << 19);
+ OUT_BATCH(((region->width - 1) << 6) |
+ (2 * region->height - 1) << 19);
OUT_BATCH(0);
OUT_BATCH(0);
@@ -376,8 +378,8 @@ static void emit_depthbuffer(struct brw_context *brw)
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
offset);
OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
- ((depth_irb->Base.Width - 1) << 6) |
- ((depth_irb->Base.Height - 1) << 19));
+ ((region->width - 1) << 6) |
+ ((region->height - 1) << 19));
OUT_BATCH(0);
if (intel->is_g4x || intel->gen >= 5)
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 8a383f5..b1ea66b 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -69,13 +69,14 @@ static void emit_depthbuffer(struct brw_context *brw)
if (stencil_mt == NULL) {
dw1 |= (BRW_SURFACE_NULL << 29);
} else {
+ struct intel_region *region = stencil_mt->region;
+
/* _NEW_STENCIL: enable stencil buffer writes */
dw1 |= ((ctx->Stencil.WriteMask != 0) << 27);
/* 3DSTATE_STENCIL_BUFFER inherits surface type and dimensions. */
dw1 |= (BRW_SURFACE_2D << 29);
- dw3 = ((srb->Base.Width - 1) << 4) |
- ((srb->Base.Height - 1) << 18);
+ dw3 = ((region->width - 1) << 4) | ((2 * region->height - 1) << 18);
}
BEGIN_BATCH(7);
@@ -107,8 +108,7 @@ static void emit_depthbuffer(struct brw_context *brw)
OUT_RELOC(region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
offset);
- OUT_BATCH(((drb->Base.Width - 1) << 4) |
- ((drb->Base.Height - 1) << 18));
+ OUT_BATCH(((region->width - 1) << 4) | ((region->height - 1) << 18));
OUT_BATCH(0);
OUT_BATCH(tile_x | (tile_y << 16));
OUT_BATCH(0);
--
1.7.7.4
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