On Fri, Jul 21, 2017 at 11:23 AM, Pohjolainen, Topi < [email protected]> wrote:
> On Fri, Jul 21, 2017 at 10:54:34AM -0700, Jason Ekstrand wrote: > > On Fri, Jul 21, 2017 at 8:00 AM, Topi Pohjolainen < > > [email protected]> wrote: > > > > > See brw_miptree_choose_tiling(). > > > > > > Signed-off-by: Topi Pohjolainen <[email protected]> > > > --- > > > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 36 > > > +++++++++++++++++++++++++++ > > > 1 file changed, 36 insertions(+) > > > > > > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > > > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > > > index 3cbdf3c938..cc0e58b74a 100644 > > > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > > > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > > > @@ -719,6 +719,29 @@ free_aux_state_map(enum isl_aux_state **state) > > > free(state); > > > } > > > > > > +static bool > > > +need_to_retile_as_linear(struct brw_context *brw, unsigned row_pitch, > > > + enum isl_tiling tiling, unsigned samples) > > > +{ > > > + if (samples > 1) > > > + return false; > > > + > > > + if (tiling == ISL_TILING_LINEAR) > > > + return false; > > > + > > > + /* If the width is much smaller than a tile, don't bother tiling. > */ > > > + if (row_pitch < 64) > > > + return true; > > > + > > > + if (ALIGN(row_pitch, 512) >= 32768) { > > > + perf_debug("row pitch %u too large to blit, falling back to > > > untiled", > > > + row_pitch); > > > + return true; > > > + } > > > > > > > You're missing the gen6 fall-back to X > > If you mean the: > > /* From the Sandybridge PRM, Volume 1, Part 2, page 32: > * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX > * or Linear." > * 128 bits per pixel translates to 16 bytes per pixel. This is necessary > * all the way back to 965, but is permitted on Gen7+. > */ > if (brw->gen < 7 && mt->cpp >= 16) > > that is provided by isl in isl_gen4_filter_tiling(). > No, I meant the one for the blitter on gen6. You handled that in it's own patch at the end. > > > > > > > + return false; > > > +} > > > + > > > static struct intel_mipmap_tree * > > > make_surface(struct brw_context *brw, GLenum target, mesa_format > format, > > > unsigned first_level, unsigned last_level, > > > @@ -767,6 +790,19 @@ make_surface(struct brw_context *brw, GLenum > target, > > > mesa_format format, > > > if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info)) > > > goto fail; > > > > > > + /* In case caller doesn't specifically request Y-tiling (needed > > > + * unconditionally for depth), check for corner cases needing > special > > > + * treatment. > > > + */ > > > + if (tiling_flags & ~ISL_TILING_Y0_BIT) { > > > + if (need_to_retile_as_linear(brw, mt->surf.row_pitch, > > > + mt->surf.tiling, > mt->surf.samples)) { > > > + init_info.tiling_flags = 1u << ISL_TILING_LINEAR; > > > > > > > We have TILING_LINEAR_BIT for this. > > > > > > > + if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info)) > > > + goto fail; > > > + } > > > + } > > > + > > > assert(mt->surf.size % mt->surf.row_pitch == 0); > > > > > > if (!bo) { > > > -- > > > 2.11.0 > > > > > > _______________________________________________ > > > mesa-dev mailing list > > > [email protected] > > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev > > > >
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