Hello list, The candidate for the Mesa 17.1.3 is now available. Currently we have: - 25 queued - 11 nominated (outstanding) - and 0 rejected patch(es)
In the current queue we have: On the loaders side - GLX/DRI3 has correct drawable invalidation while EGL has improved error handling in eglQuerySurface. The Xlib based libGL implementations now use -Bsymbolic, thus library symbols will not be overridden but third parties. An issue which can happen with tools such as apitrace. The RADV driver has received a handful of patches, including a fix to correctly advertise APU devices as integrated. Whereas i965 has seen improved HiZ handling. The etnaviv, nouveau (nvc0) and radeonsi drivers have also seen minor bugfixes. From build and integration point of view - a build fix was merged and a few requirements were loosened. In particular: SWR can now be build using C++11 compiler, as opposed to C++14 previously. While on zlib front the minimum required version is now 1.2.3 - as available in older enterprise linux distributions. Take a look at section "Mesa stable queue" for more information. Testing reports/general approval -------------------------------- Any testing reports (or general approval of the state of the branch) will be greatly appreciated. The plan is to have 17.1.3 this Saturday (17th of June), around or shortly after 14:00 GMT. If you have any questions or suggestions - be that about the current patch queue or otherwise, please go ahead. Trivial merge conflicts ----------------------- commit 15b5e5996ad1eaa88f9e684aeb7425235b7615fb Author: Chad Versace <[email protected]> i965/dri: Fix bad GL error in intel_create_winsys_renderbuffer() (cherry picked from commit 9d996e94fbbfdb3692061009f5441cf61bba36ae) commit 2a7279fa8f28ea99b2786e33f7678f92b41f69eb Author: Marek Olšák <[email protected]> radeonsi: disable the patch ID workaround on SI when the patch ID isn't used (v2) (cherry picked from commit 391673af7ad1565a5f6ac8fc2f8c9fcdd1fe9908) commit c8226d37829051b949913867e21341f4707321e9 Author: Bas Nieuwenhuizen <[email protected]> radv: Set both compute and graphics SGPRS on descriptor set flush. (cherry picked from commit 5fb8bb306534d633ceb4e33d89984718326773ba) commit ffb46c88261a2443a17740d491374266c62aea67 Author: Bas Nieuwenhuizen <[email protected]> radv: Dirty all descriptors sets when changing the pipeline. (cherry picked from commit 4415a46be2cbb752b94b62bdf5bc7d4d4bbe9fab) commit 423dab9d324e774c807403549c8e67d826af7bd4 Author: Dave Airlie <[email protected]> radv: set fmask state to all 0s when no fmask. (v2) (cherry picked from commit 51553c0beaeb91b1f2cb3292ac55573309b1d86f) Cheers, Emil Mesa stable queue ----------------- Nominated (11) ============== Ville Syrjälä (1): c1eedb4 i915: Fix wpos_tex vs. -1 comparison Jason Ekstrand (8): 86da083 i965: Flush around state base address a8ea68b i965: Take a uint64_t immediate in emit_pipe_control_write b771d9a i965: Unify the two emit_pipe_control functions 96e7b7a i965: Do an end-of-pipe sync prior to STATE_BASE_ADDRESS 314ec7b i965/blorp: Do an end-of-pipe sync around CCS ops d926127 i965: Do an end-of-pipe sync after flushes b3569e7 i965: Disable the interleaved vertex optimization when instancing f762962 i965: Set step_rate = 0 for interleaved vertex buffers Michel Dänzer (1): 176e761 gallium/util: Break recursion in pipe_resource_reference Topi Pohjolainen (1): 7b607aa i965: Add an end-of-pipe sync helper Queued (25) =========== Bas Nieuwenhuizen (3): radv: Set both compute and graphics SGPRS on descriptor set flush. radv: Dirty all descriptors sets when changing the pipeline. radv: Remove SI num RB override for occlusion queries. Brian Paul (1): xlib: fix glXGetCurrentDisplay() failure Chad Versace (1): i965/dri: Fix bad GL error in intel_create_winsys_renderbuffer() Chuck Atkins (1): configure.ac: Reduce zlib requirement from 1.2.8 to 1.2.3. Dave Airlie (3): radv: expose integrated device type for APUs. radv: set fmask state to all 0s when no fmask. (v2) glsl/lower_distance: only set max_array_access for 1D clip dist arrays Grazvydas Ignotas (1): radv: fix trace dumping for !use_ib_bos Jason Ekstrand (4): i965/blorp: Take a layer range in intel_hiz_exec i965: Move the pre-depth-clear flush/stalls to intel_hiz_exec i965: Perform HiZ flush/stall prior to HiZ resolves i965: Mark depth surfaces as needing a HiZ resolve after blitting José Fonseca (1): automake: Link all libGL.so variants with -Bsymbolic. Lucas Stach (1): etnaviv: always do cpu_fini in transfer_unmap Lyude (1): nvc0: disable BGRA8 images on Fermi Marek Olšák (3): st/mesa: don't load cached TGSI shaders on demand radeonsi: fix a GPU hang with tessellation on 2-CU configs radeonsi: disable the patch ID workaround on SI when the patch ID isn't used (v2) Nicolai Hähnle (1): radv: fewer than 8 RBs are possible Nicolas Dechesne (1): util/rand_xor: add missing include statements Tapani Pälli (1): egl: fix _eglQuerySurface in EGL_BUFFER_AGE_EXT case Thomas Hellstrom (1): dri3/GLX: Fix drawable invalidation v2 Tim Rowley (1): swr: relax c++ requirement from c++14 to c++11 Rejected (0) ============ _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
