[Mesa-dev] [PATCH 06/15] radv: remove radeon_surf_level::nblk_z

[Nicolai Hähnle]

From: Nicolai Hähnle <nicolai.haeh...@amd.com>

We're not using thick tiling modes, so we can just derive the value
ourselves.
---
 src/amd/vulkan/radv_image.c                        | 2 +-
 src/amd/vulkan/radv_radeon_winsys.h                | 1 -
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 4 ----
 3 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 8880e5c..f663e29 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -842,21 +842,21 @@ void radv_GetImageSubresourceLayout(
        int level = pSubresource->mipLevel;
        int layer = pSubresource->arrayLayer;
        struct radeon_surf *surface = &image->surface;
 
        pLayout->offset = surface->level[level].offset + 
surface->level[level].slice_size * layer;
        pLayout->rowPitch = surface->level[level].nblk_x * surface->bpe;
        pLayout->arrayPitch = surface->level[level].slice_size;
        pLayout->depthPitch = surface->level[level].slice_size;
        pLayout->size = surface->level[level].slice_size;
        if (image->type == VK_IMAGE_TYPE_3D)
-               pLayout->size *= surface->level[level].nblk_z;
+               pLayout->size *= u_minify(image->info.depth, level);
 }
 
 
 VkResult
 radv_CreateImageView(VkDevice _device,
                     const VkImageViewCreateInfo *pCreateInfo,
                     const VkAllocationCallbacks *pAllocator,
                     VkImageView *pView)
 {
        RADV_FROM_HANDLE(radv_device, device, _device);
diff --git a/src/amd/vulkan/radv_radeon_winsys.h 
b/src/amd/vulkan/radv_radeon_winsys.h
index 365ff11..b4fc781 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -162,21 +162,20 @@ struct radeon_surf_info {
        uint8_t samples;
        uint8_t levels;
        uint16_t array_size;
 };
 
 struct radeon_surf_level {
        uint64_t                    offset;
        uint64_t                    slice_size;
        uint32_t                    nblk_x;
        uint32_t                    nblk_y;
-       uint32_t                    nblk_z;
        uint32_t                    mode;
        uint64_t                    dcc_offset;
        uint64_t                    dcc_fast_clear_size;
 };
 
 
 /* surface defintions from the winsys */
 struct radeon_surf {
        /* These are inputs to the calculator. */
        uint32_t                    blk_w;
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
index ab1f952..44b1c8f 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
@@ -198,24 +198,20 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
                                     AddrSurfInfoIn,
                                     AddrSurfInfoOut);
        if (ret != ADDR_OK)
                return ret;
 
        surf_level = is_stencil ? &surf->stencil_level[level] : 
&surf->level[level];
        surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign);
        surf_level->slice_size = AddrSurfInfoOut->sliceSize;
        surf_level->nblk_x = AddrSurfInfoOut->pitch;
        surf_level->nblk_y = AddrSurfInfoOut->height;
-       if (type == RADEON_SURF_TYPE_3D)
-               surf_level->nblk_z = AddrSurfInfoOut->depth;
-       else
-               surf_level->nblk_z = 1;
 
        switch (AddrSurfInfoOut->tileMode) {
        case ADDR_TM_LINEAR_ALIGNED:
                surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
                break;
        case ADDR_TM_1D_TILED_THIN1:
                surf_level->mode = RADEON_SURF_MODE_1D;
                break;
        case ADDR_TM_2D_TILED_THIN1:
                surf_level->mode = RADEON_SURF_MODE_2D;
-- 
2.9.3

_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev