From: Marek Olšák <[email protected]>
---
src/gallium/drivers/radeonsi/si_state_shaders.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index acba3ae..d496d4a 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -393,40 +393,43 @@ static void si_set_tesseval_regs(struct si_screen
*sscreen,
* whether the "fractional odd" tessellation spacing is used.
*
* Possible VGT configurations and which state should set the register:
*
* Reg set in | VGT shader configuration | Value
* ------------------------------------------------------
* VS as VS | VS | 30
* VS as ES | ES -> GS -> VS | 30
* TES as VS | LS -> HS -> VS | 14 or 30
* TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
+ *
+ * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
*/
static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
+ struct si_shader_selector *sel,
struct si_shader *shader,
struct si_pm4_state *pm4)
{
- unsigned type = shader->selector->type;
+ unsigned type = sel->type;
if (sscreen->b.family < CHIP_POLARIS10)
return;
/* VS as VS, or VS as ES: */
if ((type == PIPE_SHADER_VERTEX &&
- !shader->key.as_ls &&
- !shader->is_gs_copy_shader) ||
+ (!shader ||
+ (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
/* TES as VS, or TES as ES: */
type == PIPE_SHADER_TESS_EVAL) {
unsigned vtx_reuse_depth = 30;
if (type == PIPE_SHADER_TESS_EVAL &&
-
shader->selector->info.properties[TGSI_PROPERTY_TES_SPACING] ==
+ sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
PIPE_TESS_SPACING_FRACTIONAL_ODD)
vtx_reuse_depth = 14;
si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
vtx_reuse_depth);
}
}
static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
{
@@ -561,21 +564,21 @@ static void si_shader_es(struct si_screen *sscreen,
struct si_shader *shader)
S_00B328_DX10_CLAMP(1) |
S_00B328_FLOAT_MODE(shader->config.float_mode));
si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
S_00B32C_USER_SGPR(num_user_sgprs) |
S_00B32C_OC_LDS_EN(oc_lds_en) |
S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
si_set_tesseval_regs(sscreen, shader->selector, pm4);
- polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
+ polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
}
/**
* Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
* geometry shader.
*/
static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
{
enum chip_class chip_class = sel->screen->b.chip_class;
unsigned gs_max_vert_out = sel->gs_max_out_vertices;
@@ -797,20 +800,23 @@ static void si_shader_gs(struct si_screen *sscreen,
struct si_shader *shader)
S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
shader->key.part.gs.es->esgs_itemsize / 4);
if (es_type == PIPE_SHADER_TESS_EVAL)
si_set_tesseval_regs(sscreen, shader->key.part.gs.es,
pm4);
+ polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
+ NULL, pm4);
+
if (shader->config.scratch_bytes_per_wave) {
fprintf(stderr, "GS: scratch buffer unsupported");
abort();
}
} else {
si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
S_00B228_VGPRS((shader->config.num_vgprs - 1) /
4) |
@@ -919,21 +925,21 @@ static void si_shader_vs(struct si_screen *sscreen,
struct si_shader *shader,
else
si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
S_028818_VTX_W0_FMT(1) |
S_028818_VPORT_X_SCALE_ENA(1) |
S_028818_VPORT_X_OFFSET_ENA(1) |
S_028818_VPORT_Y_SCALE_ENA(1) |
S_028818_VPORT_Y_OFFSET_ENA(1) |
S_028818_VPORT_Z_SCALE_ENA(1) |
S_028818_VPORT_Z_OFFSET_ENA(1));
if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
si_set_tesseval_regs(sscreen, shader->selector, pm4);
- polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
+ polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
}
static unsigned si_get_ps_num_interp(struct si_shader *ps)
{
struct tgsi_shader_info *info = &ps->selector->info;
unsigned num_colors = !!(info->colors_read & 0x0f) +
!!(info->colors_read & 0xf0);
unsigned num_interp = ps->selector->info.num_inputs +
(ps->key.part.ps.prolog.color_two_side ?
num_colors : 0);
--
2.7.4
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