From: Nicolai Hähnle <nicolai.haeh...@amd.com>
TODO add features.txt and ChangeLog
v2:
- fill in DRM version requirement
- disable on SI due to CP DMA faults
---
src/gallium/drivers/radeonsi/si_pipe.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 277fa28..9096f16 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -461,20 +461,30 @@ static int si_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
/* SI doesn't support unaligned loads.
* CIK needs DRM 2.50.0 on radeon. */
return sscreen->b.chip_class == SI ||
(sscreen->b.info.drm_major == 2 &&
sscreen->b.info.drm_minor < 50);
+ case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
+ /* Disable on SI due to VM faults in CP DMA. Enable once these
+ * faults are mitigated in software.
+ */
+ if (sscreen->b.chip_class >= CIK &&
+ sscreen->b.info.drm_major == 3 &&
+ sscreen->b.info.drm_minor >= 13)
+ return RADEON_SPARSE_PAGE_SIZE;
+ return 0;
+
/* Unsupported features. */
case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
case PIPE_CAP_USER_VERTEX_BUFFERS:
case PIPE_CAP_FAKE_SW_MSAA:
case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
case PIPE_CAP_VERTEXID_NOBASE:
case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
case PIPE_CAP_TGSI_VOTE:
--
2.9.3
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