From: Marek Olšák <[email protected]> --- src/amd/common/gfx9d.h | 4 ++++ src/gallium/drivers/radeonsi/si_state.c | 38 +++++++++++++++++++++++++++------ 2 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/src/amd/common/gfx9d.h b/src/amd/common/gfx9d.h index 1bc11b1..797bdcc 100644 --- a/src/amd/common/gfx9d.h +++ b/src/amd/common/gfx9d.h @@ -7094,20 +7094,24 @@ #define S_028C40_LOAD_COLLISION_WAVEID(x) (((unsigned)(x) & 0x1) << 2) #define G_028C40_LOAD_COLLISION_WAVEID(x) (((x) >> 2) & 0x1) #define C_028C40_LOAD_COLLISION_WAVEID 0xFFFFFFFB #define S_028C40_LOAD_INTRAWAVE_COLLISION(x) (((unsigned)(x) & 0x1) << 3) #define G_028C40_LOAD_INTRAWAVE_COLLISION(x) (((x) >> 3) & 0x1) #define C_028C40_LOAD_INTRAWAVE_COLLISION 0xFFFFFFF7 #define R_028C44_PA_SC_BINNER_CNTL_0 0x028C44 #define S_028C44_BINNING_MODE(x) (((unsigned)(x) & 0x03) << 0) #define G_028C44_BINNING_MODE(x) (((x) >> 0) & 0x03) #define C_028C44_BINNING_MODE 0xFFFFFFFC +#define V_028C44_BINNING_ALLOWED 0 +#define V_028C44_FORCE_BINNING_ON 1 +#define V_028C44_DISABLE_BINNING_USE_NEW_SC 2 +#define V_028C44_DISABLE_BINNING_USE_LEGACY_SC 3 #define S_028C44_BIN_SIZE_X(x) (((unsigned)(x) & 0x1) << 2) #define G_028C44_BIN_SIZE_X(x) (((x) >> 2) & 0x1) #define C_028C44_BIN_SIZE_X 0xFFFFFFFB #define S_028C44_BIN_SIZE_Y(x) (((unsigned)(x) & 0x1) << 3) #define G_028C44_BIN_SIZE_Y(x) (((x) >> 3) & 0x1) #define C_028C44_BIN_SIZE_Y 0xFFFFFFF7 #define S_028C44_BIN_SIZE_X_EXTEND(x) (((unsigned)(x) & 0x07) << 4) #define G_028C44_BIN_SIZE_X_EXTEND(x) (((x) >> 4) & 0x07) #define C_028C44_BIN_SIZE_X_EXTEND 0xFFFFFF8F #define S_028C44_BIN_SIZE_Y_EXTEND(x) (((unsigned)(x) & 0x07) << 7) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 4cd0494..fa69b34 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -19,20 +19,21 @@ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Christian König <[email protected]> */ #include "si_pipe.h" #include "sid.h" +#include "gfx9d.h" #include "radeon/r600_cs.h" #include "radeon/r600_query.h" #include "util/u_dual_blend.h" #include "util/u_format.h" #include "util/u_format_s3tc.h" #include "util/u_memory.h" #include "util/u_resource.h" #include "util/u_upload_mgr.h" @@ -4123,36 +4124,46 @@ static void si_init_config(struct si_context *sctx) S_028230_ER_LINE_TB(0xA) | S_028230_ER_LINE_BT(0xA)); /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */ si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0); si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0); si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0); si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0); - si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0); - si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0); - si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0); + if (sctx->b.chip_class >= GFX9) { + si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0); + si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0); + si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0); + } else { + si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0); + si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0); + si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0); + } if (sctx->b.chip_class >= CIK) { /* If this is 0, Bonaire can hang even if GS isn't being used. * Other chips are unaffected. These are suboptimal values, * but we don't use on-chip GS. */ si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL, S_028A44_ES_VERTS_PER_SUBGRP(64) | S_028A44_GS_PRIMS_PER_SUBGRP(4)); - si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff)); - si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0); - si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff)); + if (sctx->b.chip_class >= GFX9) { + si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff)); + } else { + si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff)); + si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0); + si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff)); + } si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff)); if (sscreen->b.info.num_good_compute_units / (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) { /* Too few available compute units per SH. Disallowing * VS to run on CU0 could hurt us more than late VS * allocation would help. * * LATE_ALLOC_VS = 2 is the highest safe number. */ @@ -4202,13 +4213,28 @@ static void si_init_config(struct si_context *sctx) if (sctx->b.family == CHIP_STONEY) si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0); si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8); if (sctx->b.chip_class >= CIK) si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40); si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ, RADEON_PRIO_BORDER_COLORS); + if (sctx->b.chip_class >= GFX9) { + si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL, 0); + si_pm4_set_reg(pm4, R_028064_DB_RENDER_FILTER, 0); + /* TODO: We can use this to disable RBs for rendering to GART: */ + si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0); + si_pm4_set_reg(pm4, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0); + /* TODO: Enable the binner: */ + si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0, + S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC)); + si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1, 0); + si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, + S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1)); + si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0); + } + si_pm4_upload_indirect_buffer(sctx, pm4); sctx->init_config = pm4; } -- 2.7.4 _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
