From: Dave Airlie <[email protected]> In order to get isinf(NaN) correct, at least radv can't use an unordered equals which feq has to be for us, this passes isinf to the backend and let's it sort it out as it pleases. This turns lowering on for i965 only as it's the only other spir-v consumer than radv.
v2: use lower_isinf and add algebraic lowering for it (Jason) Signed-off-by: Dave Airlie <[email protected]> --- src/compiler/nir/nir.h | 1 + src/compiler/nir/nir_opcodes.py | 3 +++ src/compiler/nir/nir_opt_algebraic.py | 3 +++ src/compiler/spirv/vtn_alu.c | 3 +-- src/intel/compiler/brw_compiler.c | 1 + 5 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 57b8be3..a43ad24 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -1777,6 +1777,7 @@ typedef struct nir_shader_compiler_options { bool lower_bitfield_insert; bool lower_uadd_carry; bool lower_usub_borrow; + bool lower_isinf; /** lowers fneg and ineg to fsub and isub. */ bool lower_negate; /** lowers fsub and isub to fadd+fneg and iadd+ineg. */ diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py index 52868d5..f6287f2 100644 --- a/src/compiler/nir/nir_opcodes.py +++ b/src/compiler/nir/nir_opcodes.py @@ -203,6 +203,9 @@ unop("fquantize2f16", tfloat, "(fabs(src0) < ldexpf(1.0, -14)) ? copysignf(0.0f, unop("fsin", tfloat, "bit_size == 64 ? sin(src0) : sinf(src0)") unop("fcos", tfloat, "bit_size == 64 ? cos(src0) : cosf(src0)") +# isinf. + +unop_convert("isinf", tbool, tfloat, "isinf(src0)") # Partial derivatives. diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index 49c1460..61bf551 100644 --- a/src/compiler/nir/nir_opt_algebraic.py +++ b/src/compiler/nir/nir_opt_algebraic.py @@ -305,6 +305,9 @@ optimizations = [ (('fabs', ('b2f', a)), ('b2f', a)), (('iabs', ('b2i', a)), ('b2i', a)), + # isinf + (('isinf', a), ('feq', ('fabs', a), float('inf')), 'options->lower_isinf'), + # Packing and then unpacking does nothing (('unpack_64_2x32_split_x', ('pack_64_2x32_split', a, b)), a), (('unpack_64_2x32_split_y', ('pack_64_2x32_split', a, b)), b), diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 0738fe0..d3d51d1 100644 --- a/src/compiler/spirv/vtn_alu.c +++ b/src/compiler/spirv/vtn_alu.c @@ -447,8 +447,7 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, break; case SpvOpIsInf: - val->ssa->def = nir_feq(&b->nb, nir_fabs(&b->nb, src[0]), - nir_imm_float(&b->nb, INFINITY)); + val->ssa->def = nir_isinf(&b->nb, src[0]); break; case SpvOpFUnordEqual: diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index cd9473f..abdf53d 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -40,6 +40,7 @@ .lower_uadd_carry = true, \ .lower_usub_borrow = true, \ .lower_fdiv = true, \ + .lower_isinf = true, \ .lower_flrp64 = true, \ .native_integers = true, \ .use_interpolated_input_intrinsics = true, \ -- 2.9.3 _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
