On Fri, Mar 17, 2017 at 1:04 AM, Dave Airlie <[email protected]> wrote: > From: Dave Airlie <[email protected]> > > In order to get isinf(NaN) correct, at least radv can't > use an unordered equals which feq has to be for us, this
Why do we have to use an unordered equal normally? SPIR-V has both ordered and unordered compares. I can't find anything in the vulkan SPIR-V environment that relaxes that. > passes isinf to the backend and let's it sort it out as it > pleases. > > Signed-off-by: Dave Airlie <[email protected]> > --- > src/compiler/nir/nir.h | 1 + > src/compiler/nir/nir_opcodes.py | 2 +- > src/compiler/spirv/vtn_alu.c | 7 +++++-- > 3 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h > index 57b8be3..bcdca4b 100644 > --- a/src/compiler/nir/nir.h > +++ b/src/compiler/nir/nir.h > @@ -1777,6 +1777,7 @@ typedef struct nir_shader_compiler_options { > bool lower_bitfield_insert; > bool lower_uadd_carry; > bool lower_usub_borrow; > + bool use_isinf; > /** lowers fneg and ineg to fsub and isub. */ > bool lower_negate; > /** lowers fsub and isub to fadd+fneg and iadd+ineg. */ > diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py > index 52868d5..7387208 100644 > --- a/src/compiler/nir/nir_opcodes.py > +++ b/src/compiler/nir/nir_opcodes.py > @@ -203,7 +203,7 @@ unop("fquantize2f16", tfloat, "(fabs(src0) < ldexpf(1.0, > -14)) ? copysignf(0.0f, > unop("fsin", tfloat, "bit_size == 64 ? sin(src0) : sinf(src0)") > unop("fcos", tfloat, "bit_size == 64 ? cos(src0) : cosf(src0)") > > - > +unop_convert("isinf", tbool, tfloat, "isinf(src0)") > # Partial derivatives. > > > diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c > index 0738fe0..79f51e7 100644 > --- a/src/compiler/spirv/vtn_alu.c > +++ b/src/compiler/spirv/vtn_alu.c > @@ -447,8 +447,11 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, > break; > > case SpvOpIsInf: > - val->ssa->def = nir_feq(&b->nb, nir_fabs(&b->nb, src[0]), > - nir_imm_float(&b->nb, INFINITY)); > + if (b->shader->options->use_isinf) > + val->ssa->def = nir_isinf(&b->nb, src[0]); > + else > + val->ssa->def = nir_feq(&b->nb, nir_fabs(&b->nb, src[0]), > + nir_imm_float(&b->nb, INFINITY)); > break; > > case SpvOpFUnordEqual: > -- > 2.9.3 > > _______________________________________________ > mesa-dev mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
