Hi, These new TGSI opcodes are for better code generation in drivers. If you know the mipmap level or LOD is 0, you don't have to pass 0 to texture instructions on hardware that has dedicated instructions for level-zero fetches. This saves a temporary register that is usually required for the level or LOD parameter.
This change surprisingly reduces VGPR register spilling for DiRT Showdown on radeonsi, but that doesn't seem to have a visible effect on performance. We can't make this improvement at the LLVM level though. Note that TXF with an MSAA target and TG4 already imply level = 0. Please review. Marek _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
