From: Marek Olšák <[email protected]>
---
src/amd/common/ac_llvm_build.c | 14 ++++++++++++++
src/amd/common/ac_llvm_build.h | 1 +
src/gallium/drivers/radeonsi/si_shader.c | 10 +++++-----
src/gallium/drivers/radeonsi/si_shader_internal.h | 3 ---
src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 17 +----------------
5 files changed, 21 insertions(+), 24 deletions(-)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 20216a7..7e8552b 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -756,10 +756,24 @@ ac_emit_sendmsg(struct ac_llvm_context *ctx,
uint32_t msg,
LLVMValueRef wave_id)
{
LLVMValueRef args[2];
const char *intr_name = (HAVE_LLVM < 0x0400) ? "llvm.SI.sendmsg" :
"llvm.amdgcn.s.sendmsg";
args[0] = LLVMConstInt(ctx->i32, msg, false);
args[1] = wave_id;
ac_emit_llvm_intrinsic(ctx, intr_name, ctx->voidt,
args, 2, 0);
}
+
+LLVMValueRef ac_emit_clamp(struct ac_llvm_context *ctx, LLVMValueRef value)
+{
+ const char *intr = HAVE_LLVM >= 0x0308 ? "llvm.AMDGPU.clamp." :
+ "llvm.AMDIL.clamp.";
+ LLVMValueRef args[3] = {
+ value,
+ LLVMConstReal(ctx->f32, 0),
+ LLVMConstReal(ctx->f32, 1),
+ };
+
+ return ac_emit_llvm_intrinsic(ctx, intr, ctx->f32, args, 3,
+ AC_FUNC_ATTR_READNONE);
+}
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index e88874a..d24c931 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -174,16 +174,17 @@ ac_emit_ddxy(struct ac_llvm_context *ctx,
#define AC_SENDMSG_GS_DONE 3
#define AC_SENDMSG_GS_OP_NOP (0 << 4)
#define AC_SENDMSG_GS_OP_CUT (1 << 4)
#define AC_SENDMSG_GS_OP_EMIT (2 << 4)
#define AC_SENDMSG_GS_OP_EMIT_CUT (3 << 4)
void ac_emit_sendmsg(struct ac_llvm_context *ctx,
uint32_t msg,
LLVMValueRef wave_id);
+LLVMValueRef ac_emit_clamp(struct ac_llvm_context *ctx, LLVMValueRef value);
#ifdef __cplusplus
}
#endif
#endif
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index d3e3984..a67ac82 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1011,21 +1011,21 @@ static void store_output_tcs(struct
lp_build_tgsi_context *bld_base,
lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
LLVMValueRef value = dst[chan_index];
if (inst->Instruction.Saturate)
- value = si_llvm_saturate(bld_base, value);
+ value = ac_emit_clamp(&ctx->ac, value);
lds_store(bld_base, chan_index, dw_addr, value);
value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
values[chan_index] = value;
if (inst->Dst[0].Register.WriteMask != 0xF) {
ac_build_tbuffer_store_dwords(&ctx->ac, buffer, value,
1,
buf_addr, base,
4 * chan_index);
@@ -1803,21 +1803,21 @@ static void si_llvm_init_export_args(struct
lp_build_tgsi_context *bld_base,
ctx->i32, pack_args, 2,
LP_FUNC_ATTR_READNONE);
args[chan + 5] =
LLVMBuildBitCast(base->gallivm->builder,
packed, ctx->f32, "");
}
break;
case V_028714_SPI_SHADER_UNORM16_ABGR:
for (chan = 0; chan < 4; chan++) {
- val[chan] = si_llvm_saturate(bld_base, values[chan]);
+ val[chan] = ac_emit_clamp(&ctx->ac, values[chan]);
val[chan] = LLVMBuildFMul(builder, val[chan],
lp_build_const_float(gallivm,
65535), "");
val[chan] = LLVMBuildFAdd(builder, val[chan],
lp_build_const_float(gallivm,
0.5), "");
val[chan] = LLVMBuildFPToUI(builder, val[chan],
ctx->i32, "");
}
args[4] = uint->one; /* COMPR flag */
args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
@@ -2681,21 +2681,21 @@ static void si_llvm_emit_vs_epilogue(struct
lp_build_tgsi_context *bld_base)
cond = LLVMGetParam(ctx->main_fn,
SI_PARAM_VS_STATE_BITS);
cond = LLVMBuildTrunc(gallivm->builder, cond,
ctx->i1, "");
lp_build_if(&if_ctx, gallivm, cond);
}
for (j = 0; j < 4; j++) {
addr = ctx->outputs[i][j];
val = LLVMBuildLoad(gallivm->builder, addr, "");
- val = si_llvm_saturate(bld_base, val);
+ val = ac_emit_clamp(&ctx->ac, val);
LLVMBuildStore(gallivm->builder, val, addr);
}
}
if (cond)
lp_build_endif(&if_ctx);
}
for (i = 0; i < info->num_outputs; i++) {
outputs[i].semantic_name = info->output_semantic_name[i];
@@ -2827,21 +2827,21 @@ static void si_export_mrt_color(struct
lp_build_tgsi_context *bld_base,
unsigned samplemask_param,
bool is_last, struct si_ps_exports *exp)
{
struct si_shader_context *ctx = si_shader_context(bld_base);
struct lp_build_context *base = &bld_base->base;
int i;
/* Clamp color */
if (ctx->shader->key.part.ps.epilog.clamp_color)
for (i = 0; i < 4; i++)
- color[i] = si_llvm_saturate(bld_base, color[i]);
+ color[i] = ac_emit_clamp(&ctx->ac, color[i]);
/* Alpha to one */
if (ctx->shader->key.part.ps.epilog.alpha_to_one)
color[3] = base->one;
/* Alpha test */
if (index == 0 &&
ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
si_alpha_test(bld_base, color[3]);
@@ -4350,21 +4350,21 @@ static void tex_fetch_args(
}
/* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
* so the depth comparison value isn't clamped for Z16 and
* Z24 anymore. Do it manually here.
*
* It's unnecessary if the original texture format was
* Z32_FLOAT, but we don't know that here.
*/
if (ctx->screen->b.chip_class == VI)
- z = si_llvm_saturate(bld_base, z);
+ z = ac_emit_clamp(&ctx->ac, z);
address[count++] = z;
}
/* Pack user derivatives */
if (opcode == TGSI_OPCODE_TXD) {
int param, num_src_deriv_channels;
switch (target) {
case TGSI_TEXTURE_3D:
diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h
b/src/gallium/drivers/radeonsi/si_shader_internal.h
index 8fde6c2..a8ef523 100644
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -195,23 +195,20 @@ void si_llvm_create_func(struct si_shader_context *ctx,
void si_llvm_dispose(struct si_shader_context *ctx);
void si_llvm_finalize_module(struct si_shader_context *ctx,
bool run_verifier);
LLVMValueRef si_llvm_emit_fetch_64bit(struct lp_build_tgsi_context *bld_base,
enum tgsi_opcode_type type,
LLVMValueRef ptr,
LLVMValueRef ptr2);
-LLVMValueRef si_llvm_saturate(struct lp_build_tgsi_context *bld_base,
- LLVMValueRef value);
-
LLVMValueRef si_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_src_register *reg,
enum tgsi_opcode_type type,
unsigned swizzle);
void si_llvm_emit_store(struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_instruction *inst,
const struct tgsi_opcode_info *info,
LLVMValueRef dst[4]);
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
index c7019c1..6618009 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
@@ -945,35 +945,20 @@ static void emit_declaration(struct lp_build_tgsi_context
*bld_base,
case TGSI_FILE_MEMORY:
ctx->declare_memory_region(ctx, decl);
break;
default:
break;
}
}
-LLVMValueRef si_llvm_saturate(struct lp_build_tgsi_context *bld_base,
- LLVMValueRef value)
-{
- struct lp_build_emit_data clamp_emit_data;
-
- memset(&clamp_emit_data, 0, sizeof(clamp_emit_data));
- clamp_emit_data.arg_count = 3;
- clamp_emit_data.args[0] = value;
- clamp_emit_data.args[2] = bld_base->base.one;
- clamp_emit_data.args[1] = bld_base->base.zero;
-
- return lp_build_emit_llvm(bld_base, TGSI_OPCODE_CLAMP,
- &clamp_emit_data);
-}
-
void si_llvm_emit_store(struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_instruction *inst,
const struct tgsi_opcode_info *info,
LLVMValueRef dst[4])
{
struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = ctx->bld_base.base.gallivm;
const struct tgsi_full_dst_register *reg = &inst->Dst[0];
LLVMBuilderRef builder = ctx->bld_base.base.gallivm->builder;
LLVMValueRef temp_ptr, temp_ptr2 = NULL;
@@ -996,21 +981,21 @@ void si_llvm_emit_store(struct lp_build_tgsi_context
*bld_base,
bld_base->emit_store(bld_base, inst, info, values);
return;
}
TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) {
LLVMValueRef value = dst[chan_index];
if (tgsi_type_is_64bit(dtype) && (chan_index == 1 || chan_index
== 3))
continue;
if (inst->Instruction.Saturate)
- value = si_llvm_saturate(bld_base, value);
+ value = ac_emit_clamp(&ctx->ac, value);
if (reg->Register.File == TGSI_FILE_ADDRESS) {
temp_ptr = ctx->addrs[reg->Register.Index][chan_index];
LLVMBuildStore(builder, value, temp_ptr);
continue;
}
if (!tgsi_type_is_64bit(dtype))
value = bitcast(bld_base, TGSI_TYPE_FLOAT, value);
--
2.7.4
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