From: Marek Olšák <[email protected]>
---
src/gallium/drivers/radeonsi/si_cp_dma.c | 32 +++++++++++++++++++++-----------
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c
b/src/gallium/drivers/radeonsi/si_cp_dma.c
index fd772c5..7e5c4b2 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -123,60 +123,65 @@ static unsigned get_flush_flags(struct si_context *sctx,
enum r600_coherency coh
}
static unsigned get_tc_l2_flag(struct si_context *sctx, enum r600_coherency
coher)
{
return coher == R600_COHERENCY_SHADER &&
sctx->b.chip_class >= CIK ? CP_DMA_USE_L2 : 0;
}
static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource
*dst,
struct pipe_resource *src, unsigned byte_count,
- uint64_t remaining_size, unsigned *flags)
+ uint64_t remaining_size,
+ bool *is_first, unsigned *packet_flags)
{
/* Count memory usage in so that need_cs_space can take it into
account. */
r600_context_add_resource_size(&sctx->b.b, dst);
if (src)
r600_context_add_resource_size(&sctx->b.b, src);
si_need_cs_space(sctx);
/* This must be done after need_cs_space. */
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
(struct r600_resource*)dst,
RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
if (src)
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
(struct r600_resource*)src,
RADEON_USAGE_READ,
RADEON_PRIO_CP_DMA);
/* Flush the caches for the first copy only.
* Also wait for the previous CP DMA operations.
*/
- if (sctx->b.flags) {
+ if (sctx->b.flags)
si_emit_cache_flush(sctx);
- *flags |= CP_DMA_RAW_WAIT;
- }
+
+ if (*is_first)
+ *packet_flags |= CP_DMA_RAW_WAIT;
+
+ *is_first = false;
/* Do the synchronization after the last dma, so that all data
* is written to memory.
*/
if (byte_count == remaining_size)
- *flags |= CP_DMA_SYNC;
+ *packet_flags |= CP_DMA_SYNC;
}
static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource
*dst,
uint64_t offset, uint64_t size, unsigned value,
enum r600_coherency coher)
{
struct si_context *sctx = (struct si_context*)ctx;
unsigned tc_l2_flag = get_tc_l2_flag(sctx, coher);
unsigned flush_flags = get_flush_flags(sctx, coher);
+ bool is_first = true;
if (!size)
return;
/* Mark the buffer range of destination as valid (initialized),
* so that transfer_map knows it should wait for the GPU when mapping
* that range. */
util_range_add(&r600_resource(dst)->valid_buffer_range, offset,
offset + size);
@@ -196,21 +201,22 @@ static void si_clear_buffer(struct pipe_context *ctx,
struct pipe_resource *dst,
uint64_t va = r600_resource(dst)->gpu_address + offset;
/* Flush the caches. */
sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
SI_CONTEXT_CS_PARTIAL_FLUSH | flush_flags;
while (size) {
unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
unsigned dma_flags = tc_l2_flag | CP_DMA_CLEAR;
- si_cp_dma_prepare(sctx, dst, NULL, byte_count, size,
&dma_flags);
+ si_cp_dma_prepare(sctx, dst, NULL, byte_count, size,
+ &is_first, &dma_flags);
/* Emit the clear packet. */
si_emit_cp_dma(sctx, va, value, byte_count, dma_flags, coher);
size -= byte_count;
va += byte_count;
}
if (tc_l2_flag)
r600_resource(dst)->TC_L2_dirty = true;
@@ -219,21 +225,22 @@ static void si_clear_buffer(struct pipe_context *ctx,
struct pipe_resource *dst,
if (coher == R600_COHERENCY_SHADER)
sctx->b.num_cp_dma_calls++;
}
/**
* Realign the CP DMA engine. This must be done after a copy with an unaligned
* size.
*
* \param size Remaining size to the CP DMA alignment.
*/
-static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size)
+static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size,
+ bool *is_first)
{
uint64_t va;
unsigned dma_flags = 0;
unsigned scratch_size = CP_DMA_ALIGNMENT * 2;
assert(size < CP_DMA_ALIGNMENT);
/* Use the scratch buffer as the dummy buffer. The 3D engine should be
* idle at this point.
*/
@@ -242,36 +249,38 @@ static void si_cp_dma_realign_engine(struct si_context
*sctx, unsigned size)
r600_resource_reference(&sctx->scratch_buffer, NULL);
sctx->scratch_buffer = (struct r600_resource*)
pipe_buffer_create(&sctx->screen->b.b, 0,
PIPE_USAGE_DEFAULT, scratch_size);
if (!sctx->scratch_buffer)
return;
sctx->emit_scratch_reloc = true;
}
si_cp_dma_prepare(sctx, &sctx->scratch_buffer->b.b,
- &sctx->scratch_buffer->b.b, size, size, &dma_flags);
+ &sctx->scratch_buffer->b.b, size, size,
+ is_first, &dma_flags);
va = sctx->scratch_buffer->gpu_address;
si_emit_cp_dma(sctx, va, va + CP_DMA_ALIGNMENT, size, dma_flags,
R600_COHERENCY_SHADER);
}
void si_copy_buffer(struct si_context *sctx,
struct pipe_resource *dst, struct pipe_resource *src,
uint64_t dst_offset, uint64_t src_offset, unsigned size)
{
uint64_t main_dst_offset, main_src_offset;
unsigned skipped_size = 0;
unsigned realign_size = 0;
unsigned tc_l2_flag = get_tc_l2_flag(sctx, R600_COHERENCY_SHADER);
unsigned flush_flags = get_flush_flags(sctx, R600_COHERENCY_SHADER);
+ bool is_first = true;
if (!size)
return;
/* Mark the buffer range of destination as valid (initialized),
* so that transfer_map knows it should wait for the GPU when mapping
* that range. */
util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
dst_offset + size);
@@ -307,45 +316,46 @@ void si_copy_buffer(struct si_context *sctx,
/* This is the main part doing the copying. Src is always aligned. */
main_dst_offset = dst_offset + skipped_size;
main_src_offset = src_offset + skipped_size;
while (size) {
unsigned dma_flags = tc_l2_flag;
unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
si_cp_dma_prepare(sctx, dst, src, byte_count,
size + skipped_size + realign_size,
- &dma_flags);
+ &is_first, &dma_flags);
si_emit_cp_dma(sctx, main_dst_offset, main_src_offset,
byte_count, dma_flags, R600_COHERENCY_SHADER);
size -= byte_count;
main_src_offset += byte_count;
main_dst_offset += byte_count;
}
/* Copy the part we skipped because src wasn't aligned. */
if (skipped_size) {
unsigned dma_flags = tc_l2_flag;
si_cp_dma_prepare(sctx, dst, src, skipped_size,
skipped_size + realign_size,
- &dma_flags);
+ &is_first, &dma_flags);
si_emit_cp_dma(sctx, dst_offset, src_offset, skipped_size,
dma_flags, R600_COHERENCY_SHADER);
}
/* Finally, realign the engine if the size wasn't aligned. */
if (realign_size)
- si_cp_dma_realign_engine(sctx, realign_size);
+ si_cp_dma_realign_engine(sctx, realign_size,
+ &is_first);
if (tc_l2_flag)
r600_resource(dst)->TC_L2_dirty = true;
/* If it's not a prefetch... */
if (dst_offset != src_offset)
sctx->b.num_cp_dma_calls++;
}
void si_init_cp_dma_functions(struct si_context *sctx)
--
2.7.4
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