From: Marek Olšák <[email protected]>
Caches are always flushed at IB boundary.
---
src/gallium/drivers/radeonsi/si_state.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 443dc37..04b57dc 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3407,28 +3407,27 @@ static void si_memory_barrier(struct pipe_context *ctx,
unsigned flags)
sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
/* Indices are read through TC L2 since VI. */
if (sctx->screen->b.chip_class <= CIK)
sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
}
if (flags & PIPE_BARRIER_FRAMEBUFFER)
sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
- if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
- PIPE_BARRIER_FRAMEBUFFER |
+ if (flags & (PIPE_BARRIER_FRAMEBUFFER |
PIPE_BARRIER_INDIRECT_BUFFER)) {
/* Not sure if INV_GLOBAL_L2 is the best thing here.
*
* We need to make sure that TC L1 & L2 are written back to
- * memory, because neither CPU accesses nor CB fetches consider
- * TC, but there's no need to invalidate any TC cache lines. */
+ * memory, because CB fetches don't consider TC, but there's
+ * no need to invalidate any TC cache lines. */
sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
}
}
static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
{
struct pipe_blend_state blend;
memset(&blend, 0, sizeof(blend));
blend.independent_blend_enable = true;
--
2.7.4
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