We need to shuffle the data before it is written to the URB. Also,
dvec3/4 need two vec4 slots.
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 9ddf19c..ba2c167 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -440,10 +440,21 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr)
int varying = instr->const_index[0] + const_offset->u32[0];
- src = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_F,
- instr->num_components);
-
- output_reg[varying] = dst_reg(src);
+ src_reg data;
+ if (nir_src_bit_size(instr->src[0]) == 64) {
+ src = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_DF,
+ instr->num_components);
+ data = src_reg(this, glsl_type::dvec4_type);
+ shuffle_64bit_data(dst_reg(data), src, true);
+ data = retype(data, BRW_REGISTER_TYPE_F);
+ output_reg[varying] = dst_reg(data);
+ if (instr->num_components > 2)
+ output_reg[varying + 1] = offset(dst_reg(data), 1);
+ } else {
+ src = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_F,
+ instr->num_components);
+ output_reg[varying] = dst_reg(src);
+ }
break;
}
--
2.7.4
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