This should have the side effect of enabling the ARB_compute_shader
extension on Gen8+ hardware and all Gen7 platforms that didn't
previously expose it (VLV and IVB GT1) due to the number of hardware
threads per subslice being insufficient in SIMD16 mode.
---
src/mesa/drivers/dri/i965/brw_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 1ab02ae..1121728 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -717,7 +717,7 @@ brw_initialize_cs_context_constants(struct brw_context
*brw, unsigned max_thread
* is not always true. This allows us to run more test cases, and will be
* required based on desktop GL compute shader requirements.
*/
- const int simd_size = ctx->API == API_OPENGL_CORE ? 16 : 8;
+ const int simd_size = ctx->API == API_OPENGL_CORE ? 32 : 8;
const uint32_t max_invocations = simd_size * max_threads;
ctx->Const.MaxComputeWorkGroupSize[0] = max_invocations;
--
2.7.3
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