lgtm
On Tue, May 10, 2016 at 10:34:28PM +0300, Topi Pohjolainen wrote:
> Until now mcs was associated to single sampled buffers only for
> fast clear purposes and it was therefore the responsibility of the
> clear logic to allocate the aux buffer when needed. Now that normal
> 3D render or blorp blit may render with mcs enabled also, they need
> to prepare the mcs just as well.
>
> v2: Do not enable for scanout buffers
> v3 (Ben):
> - Fix typo in commit message.
> - Check for gen < 9 and return early in brw_predraw_set_aux_buffers()
> - Check for gen < 9 and return early in intel_miptree_prepare_mcs()
> v4: Check for msaa_layput and number of samples to determine if
> lossless compression is to used. Otherwise one cannot distuingish
> between fast clear with and without compression.
>
> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
> Reviewed-by: Ben Widawsky <b...@bwidawsk.net> (v3)
> ---
> src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 2 ++
> src/mesa/drivers/dri/i965/brw_draw.c | 20 ++++++++++++++
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 40
> +++++++++++++++++++++++++++
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4 +++
> 4 files changed, 66 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> index ab2ceec..0672213 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> @@ -1881,6 +1881,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_layer);
> intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_layer);
>
> + intel_miptree_prepare_mcs(brw, dst_mt);
> +
> DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
> "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
> __func__,
> diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
> b/src/mesa/drivers/dri/i965/brw_draw.c
> index 9d034cf..dcbb681 100644
> --- a/src/mesa/drivers/dri/i965/brw_draw.c
> +++ b/src/mesa/drivers/dri/i965/brw_draw.c
> @@ -391,6 +391,25 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context
> *brw)
> }
> }
>
> +static void
> +brw_predraw_set_aux_buffers(struct brw_context *brw)
> +{
> + if (brw->gen < 9)
> + return;
> +
> + struct gl_context *ctx = &brw->ctx;
> + struct gl_framebuffer *fb = ctx->DrawBuffer;
> +
> + for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
> + struct intel_renderbuffer *irb =
> + intel_renderbuffer(fb->_ColorDrawBuffers[i]);
> +
> + if (irb) {
> + intel_miptree_prepare_mcs(brw, irb->mt);
> + }
> + }
> +}
> +
> /* May fail if out of video memory for texture or vbo upload, or on
> * fallback conditions.
> */
> @@ -438,6 +457,7 @@ brw_try_draw_prims(struct gl_context *ctx,
> _mesa_fls(ctx->VertexProgram._Current->Base.SamplersUsed);
>
> intel_prepare_render(brw);
> + brw_predraw_set_aux_buffers(brw);
>
> /* This workaround has to happen outside of brw_upload_render_state()
> * because it may flush the batchbuffer for a blit, affecting the state
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 8f6dc24..0b432ec 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -1622,6 +1622,46 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context
> *brw,
> return mt->mcs_mt;
> }
>
> +void
> +intel_miptree_prepare_mcs(struct brw_context *brw,
> + struct intel_mipmap_tree *mt)
> +{
> + if (mt->mcs_mt)
> + return;
> +
> + if (brw->gen < 9)
> + return;
> +
> + /* Single sample compression is represented re-using msaa compression
> + * layout type: "Compressed Multisampled Surfaces".
> + */
> + if (mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS || mt->num_samples > 1)
> + return;
> +
> + /* Clients are not currently capable of consuming compressed
> + * single-sampled buffers.
> + */
> + if (mt->is_scanout)
> + return;
> +
> + assert(intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) ||
> + intel_miptree_supports_lossless_compressed(brw, mt));
> +
> + /* Consider if lossless compression is supported but the needed
> + * auxiliary buffer doesn't exist yet.
> + *
> + * Failing to allocate the auxiliary buffer means running out of
> + * memory. The pointer to the aux miptree is left NULL which should
> + * signal non-compressed behavior.
> + */
> + if (!intel_miptree_alloc_non_msrt_mcs(brw, mt)) {
> + _mesa_warning(NULL,
> + "Failed to allocated aux buffer for lossless"
> + " compressed %p %u:%u %s\n",
> + mt, mt->logical_width0, mt->logical_height0,
> + _mesa_get_format_name(mt->format));
> + }
> +}
>
> /**
> * Helper for intel_miptree_alloc_hiz() that sets
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index 7f6e771..4fb5b69 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -693,6 +693,10 @@ bool
> intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
> struct intel_mipmap_tree *mt);
>
> +void
> +intel_miptree_prepare_mcs(struct brw_context *brw,
> + struct intel_mipmap_tree *mt);
> +
> enum {
> MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0,
> MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD = 1 << 1,
> --
> 2.5.5
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
--
Ben Widawsky, Intel Open Source Technology Center
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