On Sat, Mar 19, 2016 at 2:41 AM, Edward O'Callaghan
<eocallag...@alterapraxis.com> wrote:
> Signed-off-by: Edward O'Callaghan <eocallag...@alterapraxis.com>
> ---
> src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> index 910143f..4a00d92 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> @@ -229,9 +229,11 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum
> pipe_cap param)
> case PIPE_CAP_PCI_BUS:
> case PIPE_CAP_PCI_DEVICE:
> case PIPE_CAP_PCI_FUNCTION:
> - case PIPE_CAP_MSAA_MODES:
> return 0;
>
> + case PIPE_CAP_MSAA_MODES:
> + return (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1);
NVIDIA hw only supports up to MSAA 8. Also this would have to go in
the section where the other "odd" valued values are defined, above the
"enabled" and "disabled" sections.
> +
> case PIPE_CAP_VENDOR_ID:
> return 0x10de;
> case PIPE_CAP_DEVICE_ID: {
> --
> 2.5.0
>
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