URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1e6cf4639cd771c5896fb82d549cf5c5681a9f8
Author: Emil Velikov <[email protected]>
Date: Mon Nov 20 13:59:12 2017 +0000
Update version to 17.3.0-rc5
Signed-off-by: Emil Velikov <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bc213a6446e32143e3b478857d23c82d05c3f1d
Author: Kenneth Graunke <[email protected]>
Date: Thu Nov 16 22:31:27 2017 -0800
i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.
This apparently causes hangs on Broadwell, so let's back it out for now.
I think there are other PIPE_CONTROL workarounds that we're missing.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103787
(cherry picked from commit a01ba366e01b7d1cdfa6b0e6647536b10c0667ef)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=093ae29b3cd3a5ed243257e42a83e736a2f2d3bc
Author: Jason Ekstrand <[email protected]>
Date: Sat Nov 11 11:52:41 2017 -0800
anv/cmd_buffer: Take bo_offset into account in fast clear state addresses
Otherwise, if the image is not bound to the start of the buffer, we're
going to be reading and writing its fast clear state in the wrong spot.
Reviewed-by: Lionel Landwerlin <[email protected]>
Cc: [email protected]
(cherry picked from commit a07f7b26198ce0f5c8799481a673754968ac5daf)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2d5439412302de14627682f87b5bc0c71d074f1
Author: Jason Ekstrand <[email protected]>
Date: Sat Nov 11 22:03:45 2017 -0800
anv/cmd_buffer: Advance the address when initializing clear colors
Found by inspection
Reviewed-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Nanley Chery <[email protected]>
Cc: [email protected]
(cherry picked from commit a6cc361e5fd2450249847d5ee8093d26ed7ff545)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3bc46f1c74b5d8ed46e827b4d0b2957f0c9d74a
Author: Anuj Phogat <[email protected]>
Date: Thu Nov 9 11:30:10 2017 -0800
i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
Number of dwords in MI_FLUSH_DW changed from 4 to 5 in gen8+.
Signed-off-by: Anuj Phogat <[email protected]>
Cc: <[email protected]>
(cherry picked from commit 1dc45d75bb3ff3085f7356b8ec658111529ff76d)
[Emil Velikov: trivial conflicts]
Signed-off-by: Emil Velikov <[email protected]>
Conflicts:
src/mesa/drivers/dri/i965/intel_blit.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf0c7200bd46618e6bfda3e3e0ea85afb33fa6c0
Author: Anuj Phogat <[email protected]>
Date: Fri Nov 10 14:39:17 2017 -0800
i965: Program DWord Length in MI_FLUSH_DW
Signed-off-by: Anuj Phogat <[email protected]>
Cc: <[email protected]>
(cherry picked from commit 6165fda59b889de035b38d9a1a08ffe0da19e6a6)
Squashed with:
i965: Remove DWord length from MI_FLUSH_DW definition
Fixes: 6165fda59b8 ("i965: Program DWord Length in MI_FLUSH_DW")
Cc: <[email protected]>
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Nanley Chery <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
(cherry picked from commit 822fd2341db49cbbe813114d2d0fc1b66de4807c)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d38e92b6e9d74b35f4b65fb5839a002d68aa04e2
Author: Emil Velikov <[email protected]>
Date: Fri Nov 17 15:32:47 2017 +0000
meson: explicitly disable the build system for 17.3.x
This build system is rather incomplete in the 17.3 branch, with multiple
bugs and user facing changes already addressed in master.
It's not shipped in the tarball and we don't want to receive bug reports
about 17.3, 18.0 is the release that I hope to have the meson build in
shape for.
Simply error() out, if anyone tries to use it.
Signed-off-by: Emil Velikov <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=55c492132650599bf93c069f90c2f7255f95bb64
Author: Matt Turner <[email protected]>
Date: Tue Nov 14 11:24:08 2017 -0800
Revert "intel/fs: Use a pure vertical stride for large register strides"
This reverts commit e8c9e65185de3e821e1e482e77906d1d51efa3ec.
With the actual bug fixed (by commit 6ac2d1690192), this is not
necessary. I'm doubtful of its correctness in any case.
(cherry picked from commit a31d0382084c8aa860ffcef9b12592c5c44e192f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=78a7e2a2d41e72ddfc4371ce70c1b52d1f9cf641
Author: Matt Turner <[email protected]>
Date: Wed Nov 8 15:14:19 2017 -0800
i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK
Fixes the following tests on CHV, BXT, and GLK:
KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot
dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_int64
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103115
(cherry picked from commit cfcfa0b9cd1b1d563a988b1250950057c4612ac9)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3be7bb6741222e1fab6a3a872acfd527acc14f11
Author: Matt Turner <[email protected]>
Date: Fri Nov 10 14:00:24 2017 -0800
i965/fs: Fix extract_i8/u8 to a 64-bit destination
The MOV instruction can extract bytes to words/double words, and
words/double words to quadwords, but not byte to quadwords.
For unsigned byte to quadword, we can read them as words and AND off the
high byte and extract to quadword in one instruction. For signed bytes,
we need to first sign extend to word and the sign extend that word to a
quadword.
Fixes the following test on CHV, BXT, and GLK:
KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103628
Reviewed-by: Jason Ekstrand <[email protected]>
(cherry picked from commit 6ac2d16901927013393f873a34c717ece5014c1a)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f539ea0e8bf87d5c0fc244e2a044e7a819025348
Author: Nicolai Hähnle <[email protected]>
Date: Wed Nov 15 19:34:00 2017 +0100
tgsi/exec: fix LDEXP in softpipe
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103128
Fixes: cad959d90145 ("gallium: add LDEXP TGSI instruction and corresponding
cap")
Reviewed-by: Brian Paul <[email protected]>
(cherry picked from commit f3fa3b0d95c712c00318ca5601433bce1b82432d)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4f186d3aee41ee37e9d9196642275560ff0f178
Author: Derek Foreman <[email protected]>
Date: Mon Oct 30 15:52:22 2017 -0500
egl/wayland: Add a fallback when fourcc query isn't supported
When queryImage doesn't support __DRI_IMAGE_ATTRIB_FOURCC wayland clients
will die with a NULL derefence in wl_proxy_add_listener.
Attempt to provide a simple fallback to keep ancient systems working.
Fixes: 6595c699511 ("egl/wayland: Remove more surface specifics from
create_wl_buffer")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103519
Signed-off-by: Derek Foreman <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Acked-by: Daniel Stone <[email protected]>
Reviewed-by: Eric Engestrom <[email protected]>
(cherry picked from commit 0db36caa192b129cb4f22d152f82f38fcf6f06d4)
Squashed with:
egl: fix var type
queryImage() takes an `int*`; compiler is warning about the
signed<->unsigned pointer mismatch.
Fixes: 0db36caa192b129cb4f2 "egl/wayland: Add a fallback when fourcc
query isn't supported"
Signed-off-by: Eric Engestrom <[email protected]>
Reviewed-by: Frank Binns <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Reviewed-by: Derek Foreman <[email protected]>
(cherry picked from commit ca95d7ad4e1b900eb3d559ed5bda0b96b232961d)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8269b7ec4b67623b70f0b4e13813c3843f15d3a5
Author: Bas Nieuwenhuizen <[email protected]>
Date: Mon Nov 13 23:26:32 2017 +0100
radv: Free temporary syncobj after waiting on it.
Otherwise we leak it.
Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)"
Reviewed-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 7c255788637b8fdfc31aca5f7891f39a110c5cb2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=577af89bd13e69541329136138a19e043bc63a17
Author: Bas Nieuwenhuizen <[email protected]>
Date: Mon Nov 13 23:18:19 2017 +0100
radv: Free syncobj with multiple imports.
Otherwise we can leak the old syncobj.
Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)"
Reviewed-by: Dave Airlie <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 917d3b43f2b206ccf036542aa1c39f1dbdd84f62)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=040c0df11dbc43017700a15f94439bd49c5d26b7
Author: Thomas Hellstrom <[email protected]>
Date: Tue Sep 19 19:41:22 2017 +0200
loader/dri3: Improve dri3 thread-safety
It turned out that with recent changes that call into dri3 from glFinish(),
it appears like different thread end up waiting for X events simultaneously,
causing deadlocks since they steal events from eachoter and update the dri3
counters behind eachothers backs.
This patch intends to improve on that. It allows at most one thread at a
time to wait on events for a single drawable. If another thread intends to
do the same, it's put to sleep until the first thread finishes waiting, and
then it rechecks counters and optionally retries the waiting. Threads that
poll for X events never pulls X events off the event queue if there are
other threads waiting for events on that drawable. Counters in the
dri3 drawable structure are protected by a mutex. Finally, the mutex we
introduce is never held while waiting for the X server to avoid
unnecessary stalls.
This does not make dri3 drawables completely thread-safe but at least it's a
first step.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102358
Fixes: d5ba75f8881 "st/dri2 Plumb the flush_swapbuffer functionality
through to dri3"
Signed-off-by: Thomas Hellstrom <[email protected]>
Acked-by: Nicolai Hähnle <[email protected]>
(cherry picked from commit 54a58b2856377e18ea6a42706bea0304a8d7845e)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=699ff16e54556e1875768b3790aec589d22b7af5
Author: Kenneth Graunke <[email protected]>
Date: Fri Nov 10 15:36:22 2017 -0800
intel/tools: Fix detection of enabled shader stages.
We renamed "Function Enable" to "Enable", which broke our detection
of whether shaders are enabled or not. So, we'd see a bunch of HS/DS
packets with program offsets of 0, and think that was a valid TCS/TES.
Fixes: c032cae9ff77e (genxml: Rename "Function Enable" to "Enable".)
Reviewed-by: Lionel Landwerlin <[email protected]>
(cherry picked from commit 9a0465b3a3a1a6e8beda7a59506c2e1a1aae776f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2d020336cf5805d3428634bdc04bc7c3acd7bfc
Author: Kenneth Graunke <[email protected]>
Date: Wed Nov 15 22:40:16 2017 -0800
i965: Upload invariant state once at the start of the batch on Gen4-5.
We want to emit invariant state at the start of a render batch. In the
past, this more or less happened: a new batch flagged BRW_NEW_CONTEXT
(because we don't have hardware contexts), which triggered the
brw_invariant_state atom. So, it would be emitted before any 3D
drawing. (Technically, there might be some BLT commands in the batch
because Gen4-5 have a single combined render/BLT ring, but that should
be harmless).
With the advent of BLORP, this broke. The first item in a batch might
be a BLORP operation, which bypasses the normal draw upload path. So,
we need to ensure invariant state happens first. To do that, we just
upload it when creating a new batch. On Gen6+ we'd need to worry about
whether it's a RENDER or BLT batch, but because we have a combined ring,
this approach should work fine on Gen4-5.
Seems to fix GPU hangs when playing hardware accelerated video with
mpv -hwdec=vaapi on Ironlake.
Cc: [email protected]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103529
Reviewed-by: Jason Ekstrand <[email protected]>
(cherry picked from commit 8f91aa35a54e127b68415376ef2b577ea8fc30f9)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ed01c0a5707e001d4fba3771f2b0e811dae232c
Author: Kenneth Graunke <[email protected]>
Date: Tue Nov 14 15:24:36 2017 -0800
i965: Implement another VF cache invalidate workaround on Gen8+.
...and provide a better citation for the existing one.
v2:
- Apply the workaround to Gen8 too, as intended (caught by Topi).
- Restructure to add bits instead of an extra flush (based on a similar
patch by Rafael Antognolli).
Cc: [email protected]
Reviewed-by: Rafael Antognolli <[email protected]>
(cherry picked from commit 8d48671492412e04c18651a779cabacf30ed0afe)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=957c66de1c0b48ee5959a81deeafe990edd997fa
Author: Tim Rowley <[email protected]>
Date: Mon Nov 13 18:39:38 2017 -0600
swr/rast: Faster emulated simd16 permute
Speed up simd16 frontend (default) on avx/avx2 platforms;
fixes performance regression caused by switch to simdlib.
Reviewed-by: Bruce Cherniak <[email protected]>
Cc: [email protected]
(cherry picked from commit d8489517a572c7e5c5405ebf510db9d20b1e2591)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c79820054391b7770c6f79a8554e21cf34a075a6
Author: Tim Rowley <[email protected]>
Date: Mon Nov 13 15:11:21 2017 -0600
swr/rast: Use gather instruction for i32gather_ps on simd16/avx512
Speed up avx512 platforms; fixes performance regression caused
by swithc to simdlib.
Reviewed-by: Bruce Cherniak <[email protected]>
Cc: [email protected]
(cherry picked from commit 439904847e9c2970494c18e8c47bd6c38c0ed8ab)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3caa303cf9b1efa3627fd3cd6912a0fbc5e71e7
Author: Jason Ekstrand <[email protected]>
Date: Fri Nov 3 15:57:47 2017 -0700
i965: Add stencil buffers to cache set regardless of stencil texturing
We may access them as a texture using blorp regardless of whether or not
stencil texturing is enabled.
Reviewed-by: Kenneth Graunke <[email protected]>
Cc: [email protected]
(cherry picked from commit 6830ba0d3be8df12572622839743c41b4f294825)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fdd99c97ec6ace3537c2c30023ad0cbc6ab9199b
Author: Jason Ekstrand <[email protected]>
Date: Fri Nov 3 15:26:17 2017 -0700
i965: Use PTE MOCS for all external buffers
We were already using PTE for all render targets in case one happened to
get scanned out. However, this still wasn't 100% correct because there
are still possibly cases where we may want to texture from an external
buffer even though we don't know the caching mode. This can happen, for
instance, on buffers imported from another GPU via prime.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101691
Cc: "17.3" <[email protected]>
Tested-by: Lyude Paul <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
(cherry picked from commit d7a19d69ebc032ba7207fc97bc6f10d5bb35bb99)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9bc27748275433161b1a6c2ef08a894c3ff1203
Author: Jason Ekstrand <[email protected]>
Date: Fri Nov 3 15:20:08 2017 -0700
intel/blorp: Make the MOCS setting part of blorp_address
This makes our MOCS settings significantly more flexible.
Cc: "17.3" <[email protected]>
Tested-by: Lyude Paul <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
(cherry picked from commit bc933d0e8462871e19328f66182c35543e334013)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3bcc13539be75bf20ea1c9ede7359f57eb1c243a
Author: Jason Ekstrand <[email protected]>
Date: Fri Nov 3 15:18:45 2017 -0700
anv/blorp: Add a device parameter to blorp_surf_for_anv_image
Cc: "17.3" <[email protected]>
Tested-by: Lyude Paul <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
(cherry picked from commit deec84fd771876b5c0755293376df11bc95b473b)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9180ce378411e3486966b9ef10fb2be1157b9bf5
Author: Jason Ekstrand <[email protected]>
Date: Fri Nov 3 14:31:51 2017 -0700
intel/blorp: Use mocs.tex for depth stencil
Cc: "17.3" <[email protected]>
Tested-by: Lyude Paul <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
(cherry picked from commit 4639cc716e89c69da41c7b54fa938457000fbd4c)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=adef4109a08a42db50c9f05b6ba324ec4bf6b3e1
Author: Dave Airlie <[email protected]>
Date: Mon Nov 13 15:40:15 2017 +1000
r600: fix isoline tess factor component swapping.
As per radeonsi, the tess factor components for isolines
are reversed.
Fixes: tests/spec/arb_tessellation_shader/execution/isoline.shader_test
Cc: <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
(cherry picked from commit f3f8615d76b20ad66466b172a600e06b9a833729)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=55bc1d0a1963c876645156e03763be2739355006
Author: Dave Airlie <[email protected]>
Date: Mon Nov 13 13:05:25 2017 +1000
r600/shader: reserve first register of vertex shader.
r0 in input into vertex shaders contains things like vertexid,
we need to reserve it even if we have no inputs.
This fixes a bunch of tessellation piglits.
Cc: <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
(cherry picked from commit 50330d7115f0d5050ec3cfe6bca2b0136222e097)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a240fd6d13c26bfd8e2da5ce75068f204a634089
Author: Adam Jackson <[email protected]>
Date: Thu Nov 9 16:57:31 2017 -0500
glx/dri3: Fix passing renderType into glXCreateContext
Without this, trying to create a GLX_RGBA_FLOAT_TYPE_ARB context would
fail, because GLX_RGBA_TYPE would be a mismatch with the fbconfig.
Cc: [email protected]
Reviewed-by: Tapani Pälli <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Signed-off-by: Adam Jackson <[email protected]>
(cherry picked from commit 257edb5b9aedc9fc5d5c13eb2f48a0c11d15456f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5743c8389337e3c79d8611587914040191f75966
Author: Adam Jackson <[email protected]>
Date: Thu Nov 9 16:57:30 2017 -0500
glx/drisw: Fix glXMakeCurrent(dpy, None, ctx)
This is perfectly legal in GL 3.0+.
Fixes piglit/glx-create-context-current-no-framebuffer.
Cc: [email protected]
Reviewed-by: Tapani Pälli <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Signed-off-by: Adam Jackson <[email protected]>
(cherry picked from commit 033cfb17db85b38bc012d74f30f6c92cddf85216)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9c818ad5e1d02f579bc82f467e6b0d62f450db9
Author: Alex Smith <[email protected]>
Date: Tue Nov 7 10:52:48 2017 +0000
nir/spirv: tg4 requires a sampler
Gather operations in both GLSL and SPIR-V require a sampler. Fixes
gathers returning garbage when using separate texture/samplers (on AMD,
was using an invalid sampler descriptor).
Signed-off-by: Alex Smith <[email protected]>
Cc: "17.2 17.3" <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
(cherry picked from commit 4122d008466cef47eaa3f958924618060f4e4330)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce1a2a25d3870a3474fd5b930e8d3087fef520c5
Author: Alex Smith <[email protected]>
Date: Mon Nov 6 10:37:05 2017 +0000
spirv: Use correct type for sampled images
We should use the result type of the OpSampledImage opcode, rather than
the type of the underlying image/samplers.
This resolves an issue when using separate images and shadow samplers
with glslang. Example:
layout (...) uniform samplerShadow s0;
layout (...) uniform texture2D res0;
...
float result = textureLod(sampler2DShadow(res0, s0), uv, 0);
For this, for the combined OpSampledImage, the type of the base image
was being used (which does not have the Depth flag set, whereas the
result type does), therefore it was not being recognised as a shadow
sampler. This led to the wrong LLVM intrinsics being emitted by RADV.
Signed-off-by: Alex Smith <[email protected]>
Cc: "17.2 17.3" <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
(cherry picked from commit e9eb3c4753e4f56b03d16d8d6f71d49f1e7b97db)
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