Module: Mesa
Branch: master
Commit: 8d5994098f62c509094127aad99c6abff9cb53b1
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d5994098f62c509094127aad99c6abff9cb53b1

Author: Eric Anholt <[email protected]>
Date:   Tue Nov 14 15:52:53 2017 -0800

broadcom/vc5: Set up the padded height at surface creation time.

This centralizes the calculation in the surface, instead of in each
load/store.

---

 src/gallium/drivers/vc5/vc5_rcl.c      | 17 +++--------------
 src/gallium/drivers/vc5/vc5_resource.c | 12 ++++++++++--
 src/gallium/drivers/vc5/vc5_resource.h |  2 ++
 3 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/src/gallium/drivers/vc5/vc5_rcl.c 
b/src/gallium/drivers/vc5/vc5_rcl.c
index 5202889e59..22d6eed781 100644
--- a/src/gallium/drivers/vc5/vc5_rcl.c
+++ b/src/gallium/drivers/vc5/vc5_rcl.c
@@ -36,12 +36,8 @@ load_raw(struct vc5_cl *cl, struct pipe_surface *psurf, int 
buffer)
                 load.raw_mode = true;
                 load.buffer_to_load = buffer;
                 load.address = cl_address(rsc->bo, surf->offset);
-
-                struct vc5_resource_slice *slice =
-                        &rsc->slices[psurf->u.tex.level];
                 load.padded_height_of_output_image_in_uif_blocks =
-                        (slice->size / slice->stride) /
-                        (2 * vc5_utile_height(rsc->cpp));
+                        surf->padded_height_of_output_image_in_uif_blocks;
         }
 }
 
@@ -59,12 +55,8 @@ store_raw(struct vc5_cl *cl, struct pipe_surface *psurf, int 
buffer,
                 store.disable_colour_buffers_clear_on_write = !color_clear;
                 store.disable_z_buffer_clear_on_write = !z_clear;
                 store.disable_stencil_buffer_clear_on_write = !s_clear;
-
-                struct vc5_resource_slice *slice =
-                        &rsc->slices[psurf->u.tex.level];
                 store.padded_height_of_output_image_in_uif_blocks =
-                        (slice->size / slice->stride) /
-                        (2 * vc5_utile_height(rsc->cpp));
+                        surf->padded_height_of_output_image_in_uif_blocks;
         }
 }
 
@@ -330,11 +322,8 @@ vc5_emit_rcl(struct vc5_job *job)
 
                         zs.internal_type = surf->internal_type;
                         zs.output_image_format = surf->format;
-
-                        struct vc5_resource_slice *slice = 
&rsc->slices[psurf->u.tex.level];
-                        /* XXX */
                         zs.padded_height_of_output_image_in_uif_blocks =
-                                (slice->size / slice->stride) / (2 * 
vc5_utile_height(rsc->cpp));
+                                
surf->padded_height_of_output_image_in_uif_blocks;
 
                         assert(surf->tiling != VC5_TILING_RASTER);
                         zs.memory_format = surf->tiling;
diff --git a/src/gallium/drivers/vc5/vc5_resource.c 
b/src/gallium/drivers/vc5/vc5_resource.c
index c4d4e8c234..dad238f89f 100644
--- a/src/gallium/drivers/vc5/vc5_resource.c
+++ b/src/gallium/drivers/vc5/vc5_resource.c
@@ -715,6 +715,7 @@ vc5_create_surface(struct pipe_context *pctx,
 
         struct pipe_surface *psurf = &surface->base;
         unsigned level = surf_tmpl->u.tex.level;
+        struct vc5_resource_slice *slice = &rsc->slices[level];
 
         pipe_reference_init(&psurf->reference, 1);
         pipe_resource_reference(&psurf->texture, ptex);
@@ -727,9 +728,9 @@ vc5_create_surface(struct pipe_context *pctx,
         psurf->u.tex.first_layer = surf_tmpl->u.tex.first_layer;
         psurf->u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 
-        surface->offset = (rsc->slices[level].offset +
+        surface->offset = (slice->offset +
                            psurf->u.tex.first_layer * rsc->cube_map_stride);
-        surface->tiling = rsc->slices[level].tiling;
+        surface->tiling = slice->tiling;
         surface->format = vc5_get_rt_format(psurf->format);
 
         if (util_format_is_depth_or_stencil(psurf->format)) {
@@ -752,6 +753,13 @@ vc5_create_surface(struct pipe_context *pctx,
                 surface->internal_bpp = bpp;
         }
 
+        if (surface->tiling == VC5_TILING_UIF_NO_XOR ||
+            surface->tiling == VC5_TILING_UIF_XOR) {
+                surface->padded_height_of_output_image_in_uif_blocks =
+                        ((slice->size / slice->stride) /
+                         (2 * vc5_utile_height(rsc->cpp)));
+        }
+
         return &surface->base;
 }
 
diff --git a/src/gallium/drivers/vc5/vc5_resource.h 
b/src/gallium/drivers/vc5/vc5_resource.h
index 7d473679eb..ed464fc8d6 100644
--- a/src/gallium/drivers/vc5/vc5_resource.h
+++ b/src/gallium/drivers/vc5/vc5_resource.h
@@ -100,6 +100,8 @@ struct vc5_surface {
          * TILE_RENDERING_MODE_CONFIGURATION.
          */
         uint8_t internal_bpp;
+
+        uint32_t padded_height_of_output_image_in_uif_blocks;
 };
 
 struct vc5_resource {

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