URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb9d207ff3c97f75bd05496b33fa6e4b3143dd54
Author: Emil Velikov <[email protected]>
Date: Tue Nov 14 13:27:44 2017 +0000
Update version to 17.3.0-rc4
Signed-off-by: Emil Velikov <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d11c8abfee255991d49595be9d3150fd9d212e8
Author: Tomasz Figa <[email protected]>
Date: Tue Sep 26 17:35:56 2017 +0900
glsl: Allow precision mismatch on dead data with GLSL ES 1.00
Commit 259fc505454ea6a67aeacf6cdebf1398d9947759 added linker error for
mismatching uniform precision, as required by GLES 3.0 specification and
conformance test-suite.
Several Android applications, including Forge of Empires, have shaders
which violate this rule, on a dead varying that will be eliminated.
The problem affects a big number of applications using Cocos2D engine
and other GLES implementations accept this, this poses a serious
application compatibility issue.
Starting from GLSL ES 3.0, declarations with conflicting precision
qualifiers are explicitly prohibited. However GLSL ES 1.00 does not
clearly specify the behavior, except that
"Uniforms are defined to behave as if they are using the same storage in
the vertex and fragment processors and may be implemented this way.
If uniforms are used in both the vertex and fragment shaders, developers
should be warned if the precisions are different. Conversion of
precision should never be implicit."
The word "used" is not clear in this context and might refer to
1) declared (same as GLES 3.x)
2) referred after post-processing, or
3) linked after all optimizations are done.
Looking at existing applications, 2) or 3) seems to be widely adopted.
To avoid compatibility issues, turn the error into a warning if GLSL ES
version is lower than 3.0 and the data is dead in at least one of the
shaders.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97532
Signed-off-by: Tomasz Figa <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
(cherry picked from commit 0886be093fb871b0b6169718277e0f4d18df3ea7)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b2c15a60f8310f118f72026e56ec0d571996307
Author: Kenneth Graunke <[email protected]>
Date: Thu Nov 9 00:06:14 2017 -0800
i965: Make L3 configuration atom listen for TCS/TES program updates.
The L3 configuration code already considers the TCS and TES programs,
but failed to listen for TCS/TES program changes.
This was somehow missing.
Fixes: e9644cb1f96ccf7e ("i965: Consider tessellation in
get_pipeline_state_l3_weights.")
Reviewed-by: Francisco Jerez <[email protected]>
(cherry picked from commit b8d42cccd053e32ca048645ea7e6f901366e286d)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2036d7b385c4b5652d0af1dcf92269a6925d347
Author: Dylan Baker <[email protected]>
Date: Thu Nov 9 13:49:52 2017 -0800
autotools: Set C++ visibility flags on Intel
These flags are set for C sources, but not C++. This causes symbol
visibility leaks from the C++ parts of the Intel compiler.
Fixes: 700bebb958e93f4d ("i965: Move the back-end compiler to
src/intel/compiler")
Signed-off-by: Dylan Baker <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
(cherry picked from commit 854455498c0370e959c0bb25680641e05faea3e2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=58d0ad6ff826c6a5a053067ce94cfee4bb20bea5
Author: Roland Scheidegger <[email protected]>
Date: Tue Nov 7 01:43:51 2017 +0100
docs: Fix GL_MESA_program_debug enums
13b303ff9265b89bdd9100e32f905e9cdadfad81 added the actual enums but
didn't remove the already existing XXXX ones. (And also duplicated
the "fragment" names instead of using the "vertex" names.)
Fixes: 13b303ff9265b89bdd91 "docs: Update the list of used MESA GL enums."
Reviewed-by: Eric Engestrom <[email protected]>
Reviewed-by: Brian Paul <[email protected]>
(cherry picked from commit dd38a4ee0d0b6b7addb341fe327c245bf64903e5)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee939e7327eda174ace9f59de32e3885bb37e7cd
Author: Matt Turner <[email protected]>
Date: Fri Oct 27 18:15:46 2017 -0700
nir: Don't print swizzles when there are more than 4 components
... as can happen with various types like mat4, or else we'll smash the
stack writing past the end of components_local[].
Fixes: 5a0d3e1129b7 ("nir: Print the components referenced for split or
packed shader in/outs.")
Reviewed-by: Jason Ekstrand <[email protected]>
(cherry picked from commit 77a63d190a9bd6bcb6d6d8eb9bc734c0b18ee0e3)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e04e574c708878b231fcd4ae723727ab2dc96e6
Author: Andreas Boll <[email protected]>
Date: Wed Nov 8 15:15:08 2017 +0100
glsl: Fix typo fragement -> fragment
Fixes: 94d669b0d2f ("glsl: enforce fragment shader input restrictions in
GLSL ES 3.10")
Signed-off-by: Andreas Boll <[email protected]>
Reviewed-by: Eric Engestrom <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
(cherry picked from commit a6932faae1074445210d392a80b94fdac147b255)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9713c9d98f33424327a1cee1b00c00b44a72847
Author: Andreas Boll <[email protected]>
Date: Wed Nov 8 15:15:07 2017 +0100
broadcom/vc5: Remove unused v3d_compiler.c
Unused since original import of VC5.
Fixes: ade416d0236 ("broadcom: Add VC5 NIR compiler.")
Signed-off-by: Andreas Boll <[email protected]>
Reviewed-by: Eric Engestrom <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
(cherry picked from commit 4f29ed38f3c415a5a44d730cea1fc6fc9723f62d)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=40c905f3c269f4727193e7b1a777680740cd720d
Author: Emil Velikov <[email protected]>
Date: Tue Oct 31 18:58:10 2017 +0000
configure.ac: require xcb* for the omx/va/... when using x11 platform
Targets such as omx and va can work w/o anything X related. Mandate the
xcb* dependencies only when the X11 platform is selected.
Reported-by: Lukas Rusak <[email protected]>
Fixes: 63e11ac2b5c ("configure: error out if building VA w/o supported
platform")
Signed-off-by: Emil Velikov <[email protected]>
Reviewed-by: Eric Engestrom <[email protected]>
Tested-by: Lukas Rusak <[email protected]> (v1)
(cherry picked from commit 85a017230cacd0661570421c8e5b0619e512d33d)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7da8440504be1304ba31b51cc3472873941f357f
Author: Emil Velikov <[email protected]>
Date: Tue Oct 31 18:58:09 2017 +0000
configure.ac: loosen --enable-glvnd check to honour egl
Currently we error out when building GLVND w/o GLX.
That was the original premice before we had EGL. As the commit says,
that error should be reworked to honour both - do so.
v2: Drop noop *);; (Eric)
Reported-by: Lukas Rusak <[email protected]>
Fixes: ce562f9e3fa ("EGL: Implement the libglvnd interface for EGL (v3)")
Signed-off-by: Emil Velikov <[email protected]>
Reviewed-by: Eric Engestrom <[email protected]>
Tested-by: Lukas Rusak <[email protected]> (v1)
(cherry picked from commit b4967561c035182b64d3ae0f474d4ef281535ce1)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=797dbe4efa59dbac9a5d4fd950b596ef8cb3f222
Author: Emil Velikov <[email protected]>
Date: Mon Oct 23 13:29:30 2017 +0100
automake: intel: correctly append to the LIBADD variable
Commit 05fc62d89f5 sets the variable, yet it forgot the update the
existing reference to append (instead of assign).
Thus as-is the expat library was discarded from the link chain when
building with Android.
Fixes: 05fc62d89f5 ("automake: intel: move expat handling where it's
used")
Cc: Hongxu Jia <[email protected]>
Signed-off-by: Emil Velikov <[email protected]>
Reviewed-by: Eric Engestrom <[email protected]>
(cherry picked from commit ba414dba4f1bf354cc9494fd76e3e28b489f13a1)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2567e1de88e2989f4ae089eb534131ced589068c
Author: Timothy Arceri <[email protected]>
Date: Mon Nov 6 10:31:30 2017 +1100
i965: disable NIR linking on HSW and below
Fixes: 379b24a40d3d "i965: make use of nir linking"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103537
Reviewed-by: Iago Toral Quiroga <[email protected]>
(cherry picked from commit a9000cb860242d2d0308aec3e8fc20148a2c5eec)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3111ec7bdbe4645b3d8099fa53afc599f1f27a39
Author: Juan A. Suarez Romero <[email protected]>
Date: Fri Nov 3 18:54:21 2017 +0100
automake: include git_sha1.h.in in release tarball
Fixes:
make[2]: Leaving directory
'/home/local/mesa/mesa-17.4.0-devel/_build/sub/src'
make[2]: *** No rule to make target '../../../src/git_sha1.h.in', needed by
'git_sha1.h'. Stop.
Makefile:660: recipe for target 'all-recursive' failed
Fixes: 16be271c6ee618e79c7d "git_sha1_gen: use git_sha1.h.in on all build
systems"
Reviewed-by: Eric Engestrom <[email protected]>
Signed-off-by: Juan A. Suarez Romero <[email protected]>
(cherry picked from commit e17e8934f9e4b008bdfb4f9abd8ed4faa604c7d9)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=15ec317be8794d8c1fa5be748c00909f5c91c5ee
Author: Neil Roberts <[email protected]>
Date: Mon Oct 30 13:22:49 2017 +0100
glsl: Transform fb buffers are only active if a variable uses them
The GL spec will soon be revised to clarify that a buffer binding for
a transform feedback buffer is only required if a variable is actually
defined to use the buffer binding point. Previously a declaration for
the default transform buffer would make it require a binding even if
nothing was declared to use the default buffer.
Affects:
KHR-GL44/45.enhanced_layouts.xfb_stride_of_empty_list
KHR-GL44/45.enhanced_layouts.xfb_stride_of_empty_list_and_api
Reviewed-by: Nicolai Hähnle <[email protected]>
Cc: [email protected]
(cherry picked from commit 4dc8458cd13154daa48bd97c3f8393daf02aa351)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=53667c7f2e79ec22de537dfce1467a7cca59788d
Author: Juan A. Suarez Romero <[email protected]>
Date: Tue Oct 31 17:39:17 2017 +0000
glsl: add varying resources for arrays of complex types
This patch is mostly a patch done by Ilia Mirkin.
It fixes KHR-GL45.enhanced_layouts.varying_structure_locations.
v2: fix locations for TCS/TES/GS inputs and outputs (Ilia)
CC: Ilia Mirkin <[email protected]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103098
Reviewed-by: Nicolai Hähnle <[email protected]>
Signed-off-by: Juan A. Suarez Romero <[email protected]>
(cherry picked from commit d5a641106baae2122cc3f09b4a755077d902ee88)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=add373f7dd97b1158cbf60e384aa467c68dfd92a
Author: Jason Ekstrand <[email protected]>
Date: Sat Oct 28 09:02:14 2017 -0700
intel/nir: Use the correct indirect lowering masks in link_shaders
Previously, if we were linking a vec4 VS with a SIMD8/16 FS, we wouldn't
lower indirects on the fragment shader which is wrong. Instead of using
a single indirect mask, take advantage of our new little helper.
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Cc: [email protected]
(cherry picked from commit 951a5dc4cc29da996b54ae63eeba1915a3a65b4a)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f145df1c30072f368e6f515905000241a8af2fb
Author: Timothy Arceri <[email protected]>
Date: Wed Nov 8 10:57:21 2017 +1100
mesa: rework how we free gl_shader_program_data
When I introduced gl_shader_program_data one of the intentions was to
fix a bug where a failed linking attempt freed data required by a
currently active program. However I seem to have failed to finish
hooking up the final steps required to have the data hang around.
Here we create a fresh instance of gl_shader_program_data every
time we link. gl_program has a reference to gl_shader_program_data
so it will be freed once the program is no longer active.
Cc: "17.2 17.3" <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
Reviewed-by: Neil Roberts <[email protected]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102177
(cherry picked from commit 6a72eba755fea15a0d97abb913a6315d9d32e274)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=34ac137d3f9c56f459c20deeed2695e54d37112f
Author: Timothy Arceri <[email protected]>
Date: Wed Nov 8 11:34:10 2017 +1100
glsl: use the correct parent when allocating program data members
Cc: "17.2 17.3" <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
(cherry picked from commit 9c33533586476693a197b7179552d140d54f23f2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=26835cf6e3af7c6b51fe17e131f50e8d0114ab0a
Author: Timothy Arceri <[email protected]>
Date: Wed Nov 8 09:54:22 2017 +1100
glsl: drop cache_fallback
This turned out to be a dead end, it is much easier and less error
prone to just cache the IR used by the drivers backend e.g. TGSI or
NIR.
Cc: "17.2 17.3" <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
(cherry picked from commit cf05bb506a075c9e3b8a3c374b928ff0367c49b2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4cf6b9e7ed8a962f50b5e89ae36d6b7f3a92b96e
Author: Kenneth Graunke <[email protected]>
Date: Tue Oct 31 00:56:24 2017 -0700
i965: properly initialize brw->cs.base.stage to MESA_SHADER_COMPUTE
This has a bit of a surprising effect:
For the render pipeline, the upload_sampler_state_table atom emits
3DSTATE_BINDING_TABLE_POINTERS_XS. It tries to avoid this for compute:
if (GEN_GEN >= 7 && stage_state->stage != MESA_SHADER_COMPUTE) {
/* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
genX(emit_sampler_state_pointers_xs)(brw, stage_state);
} ...
However, we were failing to initialize brw->cs.base.stage, so it was
left as 0 (MESA_SHADER_VERTEX), causing this condition to break. We
then emitted 3DSTATE_SAMPLER_STATE_POINTERS_VS in GPGPU mode, when
trying to upload CS samplers. Nothing good can come of this.
Found by inspection while debugging a GPU hang. Jordan believes this
helps the Deus Ex: Mankind Divided benchmark mode's stability when
running with shader cache.
Cc: [email protected]
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>
(cherry picked from commit a16dc04ad51c32e5c7d136e4dd6273d983385d3f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4cc8b9b1227e2d1bc30b1c26ba6ed1a14a8e798
Author: Jason Ekstrand <[email protected]>
Date: Sat Oct 28 08:57:23 2017 -0700
intel/nir: Break the linking code into a helper in brw_nir.c
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Cc: [email protected]
(cherry picked from commit 3e63cf893f096a7263eb1856d58417dd2d170d4b)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c40cf117eef688f6a629ebfeb802bac257986559
Author: Jason Ekstrand <[email protected]>
Date: Sat Oct 28 08:50:54 2017 -0700
intel/nir: Add a helper for getting the NoIndirect mask
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Cc: [email protected]
(cherry picked from commit 7364f080f9a272323ed3491f278a1eed3eb9b1a7)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b206e3b5846e181296e11a9fc5418fd7140ab34
Author: Andreas Boll <[email protected]>
Date: Wed Nov 8 15:15:06 2017 +0100
broadcom/vc5: Add vc5_drm.h to the release tarball
Fixes: 45bb8f29571 ("broadcom: Add V3D 3.3 gallium driver called "vc5",
for BCM7268.")
Cc: 17.3 <[email protected]>
Signed-off-by: Andreas Boll <[email protected]>
Reviewed-by: Eric Engestrom <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
(cherry picked from commit 6e4d65f674a70809e6df1a4f716f874828915562)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e1698b17bcdb3227278b93b2567b80de01092e9
Author: Emil Velikov <[email protected]>
Date: Mon Oct 16 16:40:07 2017 +0100
targets/opencl: don't hardcode the icd file install to /etc/...
Use $(sysconfdir) instead of hardcoding /etc.
While the OpenCL spec expects the file in /etc, people building their
stack can override that, esp. !Linux users.
Furthermore this removes a fundamental violation, which results in the
system file being overwritten even as one explicitly sets --prefix
and/or DESTDIR.
Cc: [email protected]
Signed-off-by: Emil Velikov <[email protected]>
Reviewed-by: Francisco Jerez <[email protected]>
Reviewed-By: Aaron Watry <[email protected]>
(cherry picked from commit 0cd09585441d15ef1ff49de497008103f0b0e1ac)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c6986c3b576289a194ee066cc683eca1e592ef4
Author: Jason Ekstrand <[email protected]>
Date: Fri Sep 1 09:59:34 2017 -0700
intel/fs: Rework zero-length URB write handling
Originally we tried to handle this case based on slots_valid. However,
there are a number of ways that this can go wrong. For one, we throw
away any trailing slots which either aren't written or are set to
VARYING_SLOT_PAD. Second, even if PSIZ is a valid slot, we may not
actually write anything there. Between the lot of these, it was
possible to end up in a case where we tried to do a regular URB write
but ended up with a length of 1 which is invalid. This commit moves it
to the end and makes it based on a new boolean flag urb_written.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit 7a82ad54bb56cafaeea7f909cd9fc35542c23ba0)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=844b437034b03c030ef746fb42d62b458704afcf
Author: Jason Ekstrand <[email protected]>
Date: Mon Oct 2 20:25:11 2017 -0700
intel/fs: Mark 64-bit values as being contiguous
This isn't often a problem , when we're in a compute shader, we must
push the thread local ID so we decrement the amount of available push
space by 1 and it's no longer even and 64-bit data can, in theory, span
it. By marking those uniforms contiguous, we ensure that they never get
split in half between push and pull constants.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit 25f7453c9e6dc7c947b936bdac86680c332362bf)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e759beb906ac80343361ad1b146b7b71b0dead2f
Author: Jason Ekstrand <[email protected]>
Date: Tue Oct 17 18:56:29 2017 -0700
intel/fs: Fix integer multiplication lowering for src/dst hazards
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit d54f8ec744545673fd78f15ffce3cb4e47d4b5f1)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd5db7af2a4cd9f2cc3e98d0fefcaf2d46023069
Author: Jason Ekstrand <[email protected]>
Date: Tue Oct 17 14:45:43 2017 -0700
intel/fs: Fix MOV_INDIRECT for 64-bit values on little-core
The same workaround we need for 64-bit values on little core also takes
care of the Ivy Bridge problem and does so a bit more efficiently so we
can drop that code while we're here.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit fd1bcccc2de9ba6a1ad6171342a155091963c3b9)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9ddb51c19aa7975b92287d2cf5fde81e0b2346b
Author: Jason Ekstrand <[email protected]>
Date: Tue Oct 17 19:50:36 2017 -0700
intel/eu/reg: Add a subscript() helper
This is similar to the identically named fs_reg helper.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit 10e4feed39120072f38274b95e884422f72f360f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1060ba31f47eab396d9a9f06bf3ca723be4d8ad
Author: Jason Ekstrand <[email protected]>
Date: Thu Oct 12 16:17:03 2017 -0700
intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/all
For some reason, the any/all predicates don't work properly with SIMD32.
In particular, it appears that a SEL with a QtrCtrl of 2H doesn't read
the correct subset of the flag register and you end up getting garbage
in the second half. Work around this by using a pair of 1-wide MOVs and
scattering the result. This fixes the any/all instructions for SIMD32.
Reviewed-by: Matt Turner <[email protected]>
Cc: [email protected]
(cherry picked from commit 1b8ef49f48ae3634e4903422a9d9c11864c03cb1)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7db7159536569ff965b3a4b6e2e7181462d3a369
Author: Jason Ekstrand <[email protected]>
Date: Wed Sep 6 20:32:30 2017 -0700
intel/fs: Use an explicit D type for vote any/all/eq intrinsics
The any/all intrinsics return a boolean value so D or UD is the correct
type. Unfortunately, get_nir_dest has the annoying behavior of
returnning a float type by default. This causes format conversion which
gives us -1.0f or 0.0f in the register. If the consumer of the result
does an integer comparison to zero, it will give you the right boolean
value but if we do something more clever based on the 0/~0 assumption
for booleans, this will give the wrong value.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit 1f416630079f38110910ba796f70e2b81e9ddbf4)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a44f33f7402915e428b12288cb3df505bc3b8e4e
Author: Jason Ekstrand <[email protected]>
Date: Wed Sep 6 18:37:34 2017 -0700
intel/fs: Don't stomp f0.1 in SIMD16 ballot
In fragment shaders f0.1 is used for discards so doing ballot after a
discard can potentially cause the discard to not happen. However, we
don't support SIMD32 fragment shaders yet so this isn't a problem.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit 6c00240bc650805e0b66aa6e17dbe69bbe41e446)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5cd286710efa56002c4916cabf58a44566313f17
Author: Jason Ekstrand <[email protected]>
Date: Fri Sep 1 23:24:15 2017 -0700
intel/fs: Use ANY/ALL32 predicates in SIMD32
We have ANY/ALL32 predicates and, for the most part, they work just
fine. (See the next commit for more details.) Also, due to the way
that flag registers are handled in hardware, instruction splitting is
able to split the CMP correctly. Specifically, that hardware looks at
the execution group and knows to shift it's flag usage up correctly so a
2H instruction will write to f0.1 instead of f0.0.
Reviewed-by: Matt Turner <[email protected]>
Cc: [email protected]
(cherry picked from commit def013a863558a1f4735d82ef3dfa0f8261fa743)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e012ec8775db7591b8bcdf7e71fad96d51d7af2a
Author: Jason Ekstrand <[email protected]>
Date: Wed Sep 6 18:31:11 2017 -0700
intel/fs: Be more explicit about our placement of [un]zip
Before, we were careful to place the zip after the last of the split
instructions but did unzip on-demand. This changes things so that the
unzips go before all of the split instructions and the unzip comes
explicitly after all the split instructions. As a side-effect of this
change, we now emit the split instruction from highest SIMD group to
lowest instead of low to high. We could have kept the old behavior, but
it shouldn't matter and this made the code easier.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit 0d905597fe2997c89022c76cdf84dc4fba5eb055)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0b9db69d8245b93e33fde191bd253da8c8581b2
Author: Jason Ekstrand <[email protected]>
Date: Wed Sep 6 18:24:17 2017 -0700
intel/fs: Pass builders instead of blocks into emit_[un]zip
This makes it far more explicit where we're inserting the instructions
rather than the magic "before and after" stuff that the emit_[un]zip
helpers did based on block and inst.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit fcd4adb9d08094520fb8d118d3448b04c6ec1fd1)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9db147803950f45db7c841165f907147ac626e20
Author: Jason Ekstrand <[email protected]>
Date: Thu Nov 2 14:52:49 2017 -0700
intel/fs: Use a pure vertical stride for large register strides
Register strides higher than 4 are uncommon but they can happen. For
instance, if you have a 64-bit extract_u8 operation, we turn that into
UB -> UQ MOV with a source stride of 8. Our previous calculation would
try to generate a stride of <32;8,8>:ub which is invalid because the
maximum horizontal stride is 4. To solve this problem, we instead use a
stride of <8;1,0>. As noted in the comment, this does not work as a
destination but that's ok as very few things actually generate that
stride.
Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
Cc: [email protected]
(cherry picked from commit e8c9e65185de3e821e1e482e77906d1d51efa3ec)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b741baf8482823189cf1467f0f0bea899972166
Author: Dave Airlie <[email protected]>
Date: Fri Nov 3 04:06:35 2017 +0000
radv: add initial copy descriptor support. (v2)
It appears the latest dota2 vulkan uses this,
and we get a hang in VR mode without it.
v2: remove finishme I left in after finishing.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Andres Rodriguez <[email protected]>
Cc: "17.2 17.3" <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
(cherry picked from commit 4bcb48b8319fd8185a326bbd1f77191bddd35506)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2eff2c8768352d586e019701f106a419f6539603
Author: Dave Airlie <[email protected]>
Date: Mon Nov 6 00:35:17 2017 +0000
radv: free attachments on end command buffer.
If we allocate attachments in the begin command buffer due to the
render pass continue bit, we were leaking them.
Since renderpasses inside a cmd buffer malloc/free these properly,
and set to NULL, we just need to call free at end.
Fixes a memory leak with multithreading demo.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Cc: "17.2 17.3" <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
(cherry picked from commit f0ae06a13c1a60f58de77401f705eaf620b5b822)
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