Module: Mesa Branch: master Commit: d9ed4f6c32b4cb1d7e0f41b1f342c336e70c0af4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9ed4f6c32b4cb1d7e0f41b1f342c336e70c0af4
Author: Jason Ekstrand <[email protected]> Date: Wed Jun 14 22:28:25 2017 -0700 i965/barrier: Do the correct flushes for framebuffer access Framebuffer access includes framebuffer reads so we need to invalidate the texture cache. We do not, however, need to flush the depth cache because you cannot do bind a depth texture as an image. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> --- src/mesa/drivers/dri/i965/brw_program.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index 3743fa9b5e..c11ac871e5 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -274,7 +274,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers) PIPE_CONTROL_RENDER_TARGET_FLUSH); if (barriers & GL_FRAMEBUFFER_BARRIER_BIT) - bits |= (PIPE_CONTROL_DEPTH_CACHE_FLUSH | + bits |= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_RENDER_TARGET_FLUSH); /* Typed surface messages are handled by the render cache on IVB, so we _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
