Module: Mesa Branch: master Commit: 74e670d0a39ee0e7b26a65ee727ff9245b052878 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=74e670d0a39ee0e7b26a65ee727ff9245b052878
Author: Eric Anholt <[email protected]> Date: Mon Apr 29 11:48:22 2013 -0700 i965/vs: Do round-robin register allocation on gen6+ like we do in the FS. This will free instruction scheduling to make better choices. No statistically significant performance difference on GLB2.7 (n=93). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> --- .../drivers/dri/i965/brw_vec4_reg_allocate.cpp | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp index ac3d401..7149d46 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp @@ -102,6 +102,8 @@ brw_alloc_reg_set_for_classes(struct brw_context *brw, int class_count, int base_reg_count) { + struct intel_context *intel = &brw->intel; + /* Compute the total number of registers across all classes. */ int ra_reg_count = 0; for (int i = 0; i < class_count; i++) { @@ -112,6 +114,8 @@ brw_alloc_reg_set_for_classes(struct brw_context *brw, brw->vs.ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count); ralloc_free(brw->vs.regs); brw->vs.regs = ra_alloc_reg_set(brw, ra_reg_count); + if (intel->gen >= 6) + ra_set_allocate_round_robin(brw->vs.regs); ralloc_free(brw->vs.classes); brw->vs.classes = ralloc_array(brw, int, class_count + 1); _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
