Module: Mesa Branch: main Commit: d03cbac05af0398a8e126296829f40b9e4986d13 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d03cbac05af0398a8e126296829f40b9e4986d13
Author: Faith Ekstrand <[email protected]> Date: Mon Dec 18 18:13:56 2023 -0600 nak: Fix encoding of dsetp with RZ on SM70+ The `as_reg().is_some()` check returns false when src[1].src_ref is Zero but we want to handle that as a register case. Replace it with a match instead. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26587> --- src/nouveau/compiler/nak/encode_sm70.rs | 35 ++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/src/nouveau/compiler/nak/encode_sm70.rs b/src/nouveau/compiler/nak/encode_sm70.rs index dccfefa5f20..6f94b3528df 100644 --- a/src/nouveau/compiler/nak/encode_sm70.rs +++ b/src/nouveau/compiler/nak/encode_sm70.rs @@ -613,22 +613,25 @@ impl SM70Instr { } fn encode_dsetp(&mut self, op: &OpDSetP) { - if op.srcs[1].src_ref.as_reg().is_some() { - self.encode_alu( - 0x02a, - None, - ALUSrc::from_src(&op.srcs[0]), - ALUSrc::from_src(&op.srcs[1]), - ALUSrc::None, - ); - } else { - self.encode_alu( - 0x02a, - None, - ALUSrc::from_src(&op.srcs[0]), - ALUSrc::None, - ALUSrc::from_src(&op.srcs[1]), - ); + match op.srcs[1].src_ref { + SrcRef::Reg(_) | SrcRef::Zero => { + self.encode_alu( + 0x02a, + None, + ALUSrc::from_src(&op.srcs[0]), + ALUSrc::from_src(&op.srcs[1]), + ALUSrc::None, + ); + } + _ => { + self.encode_alu( + 0x02a, + None, + ALUSrc::from_src(&op.srcs[0]), + ALUSrc::None, + ALUSrc::from_src(&op.srcs[1]), + ); + } } self.set_pred_set_op(74..76, op.set_op);
