Module: Mesa Branch: main Commit: 5b01285cfbaa4e8663fdc5b8db959a0ff442f763 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b01285cfbaa4e8663fdc5b8db959a0ff442f763
Author: Samuel Pitoiset <[email protected]> Date: Wed Nov 29 15:43:15 2023 +0100 radv: determine if MRTZ needs to be exported via PS epilogs For GFX11 only. Signed-off-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413> --- src/amd/vulkan/radv_pipeline.c | 1 + src/amd/vulkan/radv_pipeline_graphics.c | 9 +++++++++ src/amd/vulkan/radv_shader.h | 2 ++ src/amd/vulkan/radv_shader_info.c | 9 +++++++-- 4 files changed, 19 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 5aaa5bedf33..f0b0b7268c4 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -671,6 +671,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_key .enable_mrt_output_nan_fixup = pipeline_key->ps.epilog.enable_mrt_output_nan_fixup && !stage->nir->info.internal, .no_color_export = stage->info.has_epilog, + .no_depth_export = stage->info.ps.exports_mrtz_via_epilog, .bc_optimize_for_persp = G_0286CC_PERSP_CENTER_ENA(stage->info.ps.spi_ps_input) && G_0286CC_PERSP_CENTROID_ENA(stage->info.ps.spi_ps_input), diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index b788896c642..90e184148a8 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -1933,6 +1933,15 @@ radv_generate_graphics_pipeline_key(const struct radv_device *device, const stru key.ps.epilog = radv_pipeline_generate_ps_epilog_key(device, state, disable_mrt_compaction); + if (device->physical_device->rad_info.gfx_level >= GFX11) { + /* On GFX11, alpha to coverage is exported via MRTZ when depth/stencil/samplemask are also + * exported. Though, when a PS epilog is needed and the MS state is NULL (with dynamic + * rendering), it's not possible to know the info at compile time and MRTZ needs to be + * exported in the epilog. + */ + key.ps.exports_mrtz_via_epilog = key.ps.has_epilog && !state->ms; + } + key.dynamic_patch_control_points = !!(pipeline->dynamic_states & RADV_DYNAMIC_PATCH_CONTROL_POINTS); key.dynamic_rasterization_samples = !!(pipeline->dynamic_states & RADV_DYNAMIC_RASTERIZATION_SAMPLES) || diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index aa549282b10..f7fc60bbb46 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -134,6 +134,7 @@ struct radv_pipeline_key { /* Used to export alpha through MRTZ for alpha-to-coverage (GFX11+). */ bool alpha_to_coverage_via_mrtz; + bool exports_mrtz_via_epilog; bool has_epilog; @@ -373,6 +374,7 @@ struct radv_shader_info { bool writes_stencil; bool writes_sample_mask; bool writes_mrt0_alpha; + bool exports_mrtz_via_epilog; bool has_pcoord; bool prim_id_input; bool layer_input; diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index df486b955ff..3db30920dcd 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -808,8 +808,13 @@ gather_shader_info_fs(const struct radv_device *device, const nir_shader *nir, info->has_epilog = pipeline_key->ps.has_epilog && info->ps.colors_written; - info->ps.writes_mrt0_alpha = (pipeline_key->ps.alpha_to_coverage_via_mrtz && (info->ps.color0_written & 0x8)) && - (info->ps.writes_z || info->ps.writes_stencil || info->ps.writes_sample_mask); + const bool export_alpha_and_mrtz = + (info->ps.color0_written & 0x8) && (info->ps.writes_z || info->ps.writes_stencil || info->ps.writes_sample_mask); + + info->ps.exports_mrtz_via_epilog = + info->has_epilog && pipeline_key->ps.exports_mrtz_via_epilog && export_alpha_and_mrtz; + + info->ps.writes_mrt0_alpha = pipeline_key->ps.alpha_to_coverage_via_mrtz && export_alpha_and_mrtz; info->ps.mrt0_is_dual_src = pipeline_key->ps.epilog.mrt0_is_dual_src;
