Module: Mesa Branch: main Commit: c7729effa67a6fdf420a0dbd8dc7c14ecb141cd8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7729effa67a6fdf420a0dbd8dc7c14ecb141cd8
Author: Marek Olšák <[email protected]> Date: Fri Nov 17 16:08:01 2023 -0500 radeonsi: group equal CAP cases Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26262> --- src/gallium/drivers/radeonsi/si_get.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index 672c0cce298..1ed7f474ca0 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -259,15 +259,13 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_PREFER_BACK_BUFFER_REUSE: + case PIPE_CAP_UMA: + case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF: return 0; case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: return enable_sparse ? RADEON_SPARSE_PAGE_SIZE : 0; - case PIPE_CAP_UMA: - case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF: - return 0; - case PIPE_CAP_CONTEXT_PRIORITY_MASK: if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 22)) return 0; @@ -293,6 +291,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 30; case PIPE_CAP_MAX_VARYINGS: + case PIPE_CAP_MAX_GS_INVOCATIONS: return 32; case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: @@ -311,9 +310,6 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 256; case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: return 1024; - case PIPE_CAP_MAX_GS_INVOCATIONS: - /* Even though the hw supports more, we officially wanna expose only 32. */ - return 32; case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: return 2048;
