Module: Mesa Branch: main Commit: 5932990e08e6f8126ff1b6daee3391dda2a6a1ef URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5932990e08e6f8126ff1b6daee3391dda2a6a1ef
Author: Qiang Yu <[email protected]> Date: Wed Nov 1 17:27:43 2023 +0800 aco,radv: add aco_is_nir_op_support_packed_math_16bit To be shared by radeonsi and radv. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25990> --- src/amd/compiler/aco_interface.cpp | 41 ++++++++++++++++++++++++++++++++++++++ src/amd/compiler/aco_interface.h | 5 ++++- src/amd/vulkan/radv_pipeline.c | 39 +----------------------------------- 3 files changed, 46 insertions(+), 39 deletions(-) diff --git a/src/amd/compiler/aco_interface.cpp b/src/amd/compiler/aco_interface.cpp index 757711aa0ad..76d4b13b308 100644 --- a/src/amd/compiler/aco_interface.cpp +++ b/src/amd/compiler/aco_interface.cpp @@ -436,3 +436,44 @@ aco_is_gpu_supported(const struct radeon_info* info) /* Does not support compute only cards yet. */ return info->gfx_level >= GFX6 && info->has_graphics; } + +bool +aco_nir_op_supports_packed_math_16bit(const nir_alu_instr* alu) +{ + switch (alu->op) { + case nir_op_f2f16: { + nir_shader* shader = nir_cf_node_get_function(&alu->instr.block->cf_node)->function->shader; + unsigned execution_mode = shader->info.float_controls_execution_mode; + return nir_is_rounding_mode_rtz(execution_mode, 16); + } + case nir_op_fadd: + case nir_op_fsub: + case nir_op_fmul: + case nir_op_ffma: + case nir_op_fdiv: + case nir_op_flrp: + case nir_op_fabs: + case nir_op_fneg: + case nir_op_fsat: + case nir_op_fmin: + case nir_op_fmax: + case nir_op_f2f16_rtz: + case nir_op_iabs: + case nir_op_iadd: + case nir_op_iadd_sat: + case nir_op_uadd_sat: + case nir_op_isub: + case nir_op_isub_sat: + case nir_op_usub_sat: + case nir_op_ineg: + case nir_op_imul: + case nir_op_imin: + case nir_op_imax: + case nir_op_umin: + case nir_op_umax: return true; + case nir_op_ishl: /* TODO: in NIR, these have 32bit shift operands */ + case nir_op_ishr: /* while Radeon needs 16bit operands when vectorized */ + case nir_op_ushr: + default: return false; + } +} diff --git a/src/amd/compiler/aco_interface.h b/src/amd/compiler/aco_interface.h index 16fc99770fd..85c270ba199 100644 --- a/src/amd/compiler/aco_interface.h +++ b/src/amd/compiler/aco_interface.h @@ -27,12 +27,13 @@ #include "aco_shader_info.h" +#include "nir.h" + #include "amd_family.h" #ifdef __cplusplus extern "C" { #endif -typedef struct nir_shader nir_shader; struct ac_shader_config; struct aco_shader_info; struct aco_vs_prolog_info; @@ -100,6 +101,8 @@ uint64_t aco_get_codegen_flags(); bool aco_is_gpu_supported(const struct radeon_info* info); +bool aco_nir_op_supports_packed_math_16bit(const nir_alu_instr* alu); + #ifdef __cplusplus } #endif diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 0e3a79f5307..896501fd4f1 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -489,44 +489,7 @@ opt_vectorize_callback(const nir_instr *instr, const void *_) if (bit_size != 16) return 1; - switch (alu->op) { - case nir_op_f2f16: { - nir_shader *shader = nir_cf_node_get_function(&instr->block->cf_node)->function->shader; - unsigned execution_mode = shader->info.float_controls_execution_mode; - return nir_is_rounding_mode_rtz(execution_mode, 16) ? 2 : 1; - } - case nir_op_fadd: - case nir_op_fsub: - case nir_op_fmul: - case nir_op_ffma: - case nir_op_fdiv: - case nir_op_flrp: - case nir_op_fabs: - case nir_op_fneg: - case nir_op_fsat: - case nir_op_fmin: - case nir_op_fmax: - case nir_op_f2f16_rtz: - case nir_op_iabs: - case nir_op_iadd: - case nir_op_iadd_sat: - case nir_op_uadd_sat: - case nir_op_isub: - case nir_op_isub_sat: - case nir_op_usub_sat: - case nir_op_ineg: - case nir_op_imul: - case nir_op_imin: - case nir_op_imax: - case nir_op_umin: - case nir_op_umax: - return 2; - case nir_op_ishl: /* TODO: in NIR, these have 32bit shift operands */ - case nir_op_ishr: /* while Radeon needs 16bit operands when vectorized */ - case nir_op_ushr: - default: - return 1; - } + return aco_nir_op_supports_packed_math_16bit(alu) ? 2 : 1; } static nir_component_mask_t
