Module: Mesa Branch: main Commit: a31c928c4f4e8f5da6a30bdc63a5229c32f345ac URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a31c928c4f4e8f5da6a30bdc63a5229c32f345ac
Author: Rhys Perry <[email protected]> Date: Wed Oct 4 14:33:58 2023 +0100 radv: use nir_lower_fp16_casts This correctly implements RTNE f64->f16. Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Georg Lehmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25566> --- src/amd/vulkan/radv_pipeline.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index d6581e13451..a4351836e76 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -735,6 +735,8 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_key radv_optimize_nir_algebraic( stage->nir, io_to_mem || lowered_ngg || stage->stage == MESA_SHADER_COMPUTE || stage->stage == MESA_SHADER_TASK); + NIR_PASS(_, stage->nir, nir_lower_fp16_casts, nir_lower_fp16_split_fp64); + if (stage->nir->info.bit_sizes_int & (8 | 16)) { if (gfx_level >= GFX8) { NIR_PASS(_, stage->nir, nir_convert_to_lcssa, true, true);
