Module: Mesa Branch: staging/23.3 Commit: bbf099223efa728dd5de03118bceb4ead24c71c9 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bbf099223efa728dd5de03118bceb4ead24c71c9
Author: Sagar Ghuge <[email protected]> Date: Wed Nov 8 17:33:40 2023 -0800 anv: Write timestamp using MI_FLUSH_DW on blitter On Blitter engine, we don't support PIPE_CONTROL, we have to update memory locations using the MI_FLUSH_DW command. v2: - Handle video queue (Lionel) Fixes: 056b0cb87f2 ("anv: add video engine support in various places") Fixes: 5112b421462 ("anv: Handle end of pipe with MI_FLUSH_DW on transfer queue") Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26121> (cherry picked from commit 8c9a7f77303b5acb4555a8c41b897da891fbe2da) --- .pick_status.json | 2 +- src/intel/vulkan/genX_cmd_buffer.c | 6 ++++-- src/intel/vulkan/genX_query.c | 20 +++++++++++++++----- 3 files changed, 20 insertions(+), 8 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 61a49dcb492..d6504a8ffaf 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -5184,7 +5184,7 @@ "description": "anv: Write timestamp using MI_FLUSH_DW on blitter", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "056b0cb87f2831715452f2754df8d1bc810c6155", "notes": null diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 424e917ee6a..5090e0fe1ec 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -8073,7 +8073,8 @@ void genX(cmd_emit_timestamp)(struct anv_batch *batch, * ANV_TIMESTAMP_REWRITE_COMPUTE_WALKER capture type are not set for * transfer queue. */ - if (batch->engine_class == INTEL_ENGINE_CLASS_COPY) { + if ((batch->engine_class == INTEL_ENGINE_CLASS_COPY) || + (batch->engine_class == INTEL_ENGINE_CLASS_VIDEO)) { assert(type != ANV_TIMESTAMP_CAPTURE_AT_CS_STALL && type != ANV_TIMESTAMP_REWRITE_COMPUTE_WALKER); } @@ -8087,7 +8088,8 @@ void genX(cmd_emit_timestamp)(struct anv_batch *batch, } case ANV_TIMESTAMP_CAPTURE_END_OF_PIPE: { - if (batch->engine_class == INTEL_ENGINE_CLASS_COPY) { + if ((batch->engine_class == INTEL_ENGINE_CLASS_COPY) || + (batch->engine_class == INTEL_ENGINE_CLASS_VIDEO)) { anv_batch_emit(batch, GENX(MI_FLUSH_DW), fd) { fd.PostSyncOperation = WriteTimestamp; fd.Address = addr; diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c index 69c5ac83041..1f194427669 100644 --- a/src/intel/vulkan/genX_query.c +++ b/src/intel/vulkan/genX_query.c @@ -1391,12 +1391,22 @@ void genX(CmdWriteTimestamp2)( bool cs_stall_needed = (GFX_VER == 9 && cmd_buffer->device->info->gt == 4); - genx_batch_emit_pipe_control_write - (&cmd_buffer->batch, cmd_buffer->device->info, WriteTimestamp, - anv_address_add(query_addr, 8), 0, - cs_stall_needed ? ANV_PIPE_CS_STALL_BIT : 0); - emit_query_pc_availability(cmd_buffer, query_addr, true); + if (anv_cmd_buffer_is_blitter_queue(cmd_buffer) || + anv_cmd_buffer_is_video_queue(cmd_buffer)) { + anv_batch_emit(&cmd_buffer->batch, GENX(MI_FLUSH_DW), dw) { + dw.Address = anv_address_add(query_addr, 8); + dw.PostSyncOperation = WriteTimestamp; + } + emit_query_mi_flush_availability(cmd_buffer, query_addr, true); + } else { + genx_batch_emit_pipe_control_write + (&cmd_buffer->batch, cmd_buffer->device->info, WriteTimestamp, + anv_address_add(query_addr, 8), 0, + cs_stall_needed ? ANV_PIPE_CS_STALL_BIT : 0); + emit_query_pc_availability(cmd_buffer, query_addr, true); + } + }
