Module: Mesa Branch: main Commit: 03a7cb261828b350dd9b56bd74850197ca9eba33 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=03a7cb261828b350dd9b56bd74850197ca9eba33
Author: Friedrich Vock <[email protected]> Date: Fri Nov 10 13:16:10 2023 +0100 ac/gpu_info: Manually compute L3 size for Navi33 The firmware reports no MALL cache being present, which is wrong. We later depend on correct L3 cache size values for choosing the attribute ring size, so fall back to manually computing the size. Fixes: 355242f055 ("ac/gpu_info: adjust attribute ring size for gfx11") Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26147> --- src/amd/common/ac_gpu_info.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index ac0c26b49f4..7d2f0f9eead 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -1067,7 +1067,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, info->num_sqc_per_wgp = device_info.num_sqc_per_wgp; } - if (info->gfx_level >= GFX11 && info->drm_minor >= 52) { + /* Firmware wrongly reports 0 bytes of MALL being present on Navi33. + * Work around this by manually computing cache sizes. */ + if (info->gfx_level >= GFX11 && info->drm_minor >= 52 && info->family != CHIP_NAVI33) { info->tcp_cache_size = device_info.tcp_cache_size * 1024; info->l1_cache_size = device_info.gl1c_cache_size * 1024; info->l2_cache_size = device_info.gl2c_cache_size * 1024;
