Module: Mesa Branch: main Commit: e4db19afa72b3dc2a33acc6435f714176adc6df1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4db19afa72b3dc2a33acc6435f714176adc6df1
Author: Tapani Pälli <[email protected]> Date: Mon Jul 31 10:43:15 2023 +0300 iris: add data cache flush for pre hiz op This fixes various failing Piglit tests on DG2. Cc: mesa-stable Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Sagar Ghuge <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22717> --- src/gallium/drivers/iris/iris_resolve.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c index 4a202bc7e88..c68c849c2bf 100644 --- a/src/gallium/drivers/iris/iris_resolve.c +++ b/src/gallium/drivers/iris/iris_resolve.c @@ -700,6 +700,13 @@ iris_hiz_exec(struct iris_context *ice, //DBG("%s %s to mt %p level %d layers %d-%d\n", //__func__, name, mt, level, start_layer, start_layer + num_layers - 1); + /* A data cache flush is not suggested by HW docs, but we found it to fix + * a number of failures. + */ + unsigned wa_flush = intel_device_info_is_dg2(batch->screen->devinfo) && + res->aux.usage == ISL_AUX_USAGE_HIZ_CCS ? + PIPE_CONTROL_DATA_CACHE_FLUSH : 0; + /* The following stalls and flushes are only documented to be required * for HiZ clear operations. However, they also seem to be required for * resolve operations. @@ -716,6 +723,7 @@ iris_hiz_exec(struct iris_context *ice, iris_emit_pipe_control_flush(batch, "hiz op: pre-flush", PIPE_CONTROL_DEPTH_CACHE_FLUSH | + wa_flush | PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_CS_STALL);
