Module: Mesa Branch: main Commit: d76d58cf50c9698790abc6067f7c5e6b5effe899 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d76d58cf50c9698790abc6067f7c5e6b5effe899
Author: Caio Oliveira <[email protected]> Date: Mon Oct 16 23:25:00 2023 -0700 intel/compiler: Cache issue_time information Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25841> --- src/intel/compiler/brw_schedule_instructions.cpp | 25 ++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index abe65beca01..d1d89f99513 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -94,6 +94,15 @@ public: * successors is an exit node. */ schedule_node *exit; + + /** + * How many cycles this instruction takes to issue. + * + * Instructions in gen hardware are handled one simd4 vector at a time, + * with 1 cycle per vector dispatched. Thus SIMD8 pixel shaders take 2 + * cycles to dispatch and SIMD16 (compressed) instructions take 4. + */ + int issue_time; }; /** @@ -703,13 +712,6 @@ public: virtual void calculate_deps() = 0; virtual schedule_node *choose_instruction_to_schedule() = 0; - /** - * Returns how many cycles it takes the instruction to issue. - * - * Instructions in gen hardware are handled one simd4 vector at a time, - * with 1 cycle per vector dispatched. Thus SIMD8 pixel shaders take 2 - * cycles to dispatch and SIMD16 (compressed) instructions take 4. - */ virtual int issue_time(backend_instruction *inst) = 0; virtual void count_reads_remaining(backend_instruction *inst) = 0; @@ -1046,7 +1048,7 @@ instruction_scheduler::compute_delays() { for (schedule_node *n = current.end - 1; n >= current.start; n--) { if (!n->child_count) { - n->delay = issue_time(n->inst); + n->delay = n->issue_time; } else { for (int i = 0; i < n->child_count; i++) { assert(n->children[i]->delay); @@ -1067,7 +1069,7 @@ instruction_scheduler::compute_exits() for (int i = 0; i < n->child_count; i++) { n->children[i]->unblocked_time = MAX2(n->children[i]->unblocked_time, - n->unblocked_time + issue_time(n->inst) + n->child_latency[i]); + n->unblocked_time + n->issue_time + n->child_latency[i]); } } @@ -1878,7 +1880,7 @@ instruction_scheduler::schedule(schedule_node *chosen) /* Update the clock for how soon an instruction could start after the * chosen one. */ - current.time += issue_time(chosen->inst); + current.time += chosen->issue_time; if (debug) { fprintf(stderr, "clock %4d, scheduled: ", current.time); @@ -1986,6 +1988,9 @@ instruction_scheduler::run(cfg_t *cfg) set_current_block(block); + for (schedule_node *n = current.start; n < current.end; n++) + n->issue_time = issue_time(n->inst); + calculate_deps(); compute_delays();
