Module: Mesa Branch: main Commit: bc09932ec3b7b0fe504a40df8b2f1164aded4001 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc09932ec3b7b0fe504a40df8b2f1164aded4001
Author: Samuel Pitoiset <[email protected]> Date: Mon Oct 23 19:03:22 2023 +0200 ac/registers: allow to parse GCVM_L2_PROTECTION_FAULT_STATUS To have defined bitfields for this register. Signed-off-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25855> --- src/amd/registers/gfx10.json | 20 ++++++++++++++++++++ src/amd/registers/gfx103.json | 20 ++++++++++++++++++++ src/amd/registers/gfx11.json | 21 +++++++++++++++++++++ src/amd/registers/gfx115.json | 22 ++++++++++++++++++++++ src/amd/registers/parse_kernel_headers.py | 1 + 5 files changed, 84 insertions(+) diff --git a/src/amd/registers/gfx10.json b/src/amd/registers/gfx10.json index f5f2be0162c..9258fa6f3ab 100644 --- a/src/amd/registers/gfx10.json +++ b/src/amd/registers/gfx10.json @@ -1756,6 +1756,12 @@ "name": "GB_MACROTILE_MODE15", "type_ref": "GB_MACROTILE_MODE0" }, + { + "chips": ["gfx10"], + "map": {"at": 41264, "to": "mm"}, + "name": "GCVM_L2_PROTECTION_FAULT_STATUS", + "type_ref": "GCVM_L2_PROTECTION_FAULT_STATUS" + }, { "chips": ["gfx10"], "map": {"at": 45060, "to": "mm"}, @@ -13017,6 +13023,20 @@ {"bits": [28, 31], "name": "CNTL_MODE"} ] }, + "GCVM_L2_PROTECTION_FAULT_STATUS": { + "fields": [ + {"bits": [0, 0], "name": "MORE_FAULTS"}, + {"bits": [1, 3], "name": "WALKER_ERROR"}, + {"bits": [4, 7], "name": "PERMISSION_FAULTS"}, + {"bits": [8, 8], "name": "MAPPING_ERROR"}, + {"bits": [9, 17], "name": "CID"}, + {"bits": [18, 18], "name": "RW"}, + {"bits": [19, 19], "name": "ATOMIC"}, + {"bits": [20, 23], "name": "VMID"}, + {"bits": [24, 24], "name": "VF"}, + {"bits": [25, 29], "name": "VFID"} + ] + }, "GC_ATC_L2_PERFCOUNTER0_CFG": { "fields": [ {"bits": [0, 7], "name": "PERF_SEL"}, diff --git a/src/amd/registers/gfx103.json b/src/amd/registers/gfx103.json index 2f5f1b6723d..9b505971d61 100644 --- a/src/amd/registers/gfx103.json +++ b/src/amd/registers/gfx103.json @@ -1405,6 +1405,12 @@ "name": "GB_ADDR_CONFIG", "type_ref": "GB_ADDR_CONFIG" }, + { + "chips": ["gfx103"], + "map": {"at": 41120, "to": "mm"}, + "name": "GCVM_L2_PROTECTION_FAULT_STATUS", + "type_ref": "GCVM_L2_PROTECTION_FAULT_STATUS" + }, { "chips": ["gfx103"], "map": {"at": 45060, "to": "mm"}, @@ -12908,6 +12914,20 @@ {"bits": [28, 31], "name": "CNTL_MODE"} ] }, + "GCVM_L2_PROTECTION_FAULT_STATUS": { + "fields": [ + {"bits": [0, 0], "name": "MORE_FAULTS"}, + {"bits": [1, 3], "name": "WALKER_ERROR"}, + {"bits": [4, 7], "name": "PERMISSION_FAULTS"}, + {"bits": [8, 8], "name": "MAPPING_ERROR"}, + {"bits": [9, 17], "name": "CID"}, + {"bits": [18, 18], "name": "RW"}, + {"bits": [19, 19], "name": "ATOMIC"}, + {"bits": [20, 23], "name": "VMID"}, + {"bits": [24, 24], "name": "VF"}, + {"bits": [25, 29], "name": "VFID"} + ] + }, "GDS_ATOM_BASE": { "fields": [ {"bits": [0, 15], "name": "BASE"}, diff --git a/src/amd/registers/gfx11.json b/src/amd/registers/gfx11.json index 8aa6a526f86..5f8fc95d029 100644 --- a/src/amd/registers/gfx11.json +++ b/src/amd/registers/gfx11.json @@ -1293,6 +1293,12 @@ "name": "GB_ADDR_CONFIG", "type_ref": "GB_ADDR_CONFIG" }, + { + "chips": ["gfx11"], + "map": {"at": 41120, "to": "mm"}, + "name": "GCVM_L2_PROTECTION_FAULT_STATUS", + "type_ref": "GCVM_L2_PROTECTION_FAULT_STATUS" + }, { "chips": ["gfx11"], "map": {"at": 45060, "to": "mm"}, @@ -11731,6 +11737,21 @@ {"bits": [20, 23], "name": "COMPARE_VALUE3"} ] }, + "GCVM_L2_PROTECTION_FAULT_STATUS": { + "fields": [ + {"bits": [0, 0], "name": "MORE_FAULTS"}, + {"bits": [1, 3], "name": "WALKER_ERROR"}, + {"bits": [4, 7], "name": "PERMISSION_FAULTS"}, + {"bits": [8, 8], "name": "MAPPING_ERROR"}, + {"bits": [9, 17], "name": "CID"}, + {"bits": [18, 18], "name": "RW"}, + {"bits": [19, 19], "name": "ATOMIC"}, + {"bits": [20, 23], "name": "VMID"}, + {"bits": [24, 24], "name": "VF"}, + {"bits": [25, 28], "name": "VFID"}, + {"bits": [29, 29], "name": "PRT"} + ] + }, "GDS_ATOM_BASE": { "fields": [ {"bits": [0, 11], "name": "BASE"}, diff --git a/src/amd/registers/gfx115.json b/src/amd/registers/gfx115.json index ac0dd1ba8e5..03f320a7fa6 100644 --- a/src/amd/registers/gfx115.json +++ b/src/amd/registers/gfx115.json @@ -1262,6 +1262,12 @@ "name": "GB_ADDR_CONFIG", "type_ref": "GB_ADDR_CONFIG" }, + { + "chips": ["gfx115"], + "map": {"at": 41136, "to": "mm"}, + "name": "GCVM_L2_PROTECTION_FAULT_STATUS", + "type_ref": "GCVM_L2_PROTECTION_FAULT_STATUS" + }, { "chips": ["gfx115"], "map": {"at": 45060, "to": "mm"}, @@ -11592,6 +11598,22 @@ {"bits": [20, 23], "name": "COMPARE_VALUE3"} ] }, + "GCVM_L2_PROTECTION_FAULT_STATUS": { + "fields": [ + {"bits": [0, 0], "name": "MORE_FAULTS"}, + {"bits": [1, 3], "name": "WALKER_ERROR"}, + {"bits": [4, 7], "name": "PERMISSION_FAULTS"}, + {"bits": [8, 8], "name": "MAPPING_ERROR"}, + {"bits": [9, 17], "name": "CID"}, + {"bits": [18, 18], "name": "RW"}, + {"bits": [19, 19], "name": "ATOMIC"}, + {"bits": [20, 23], "name": "VMID"}, + {"bits": [24, 24], "name": "VF"}, + {"bits": [25, 28], "name": "VFID"}, + {"bits": [29, 29], "name": "PRT"}, + {"bits": [30, 30], "name": "FED"} + ] + }, "GC_ATC_L2_PERFCOUNTER2_SELECT": { "fields": [ {"bits": [0, 9], "name": "PERF_SEL0"}, diff --git a/src/amd/registers/parse_kernel_headers.py b/src/amd/registers/parse_kernel_headers.py index 3ddabe25536..79e0f00fd0f 100644 --- a/src/amd/registers/parse_kernel_headers.py +++ b/src/amd/registers/parse_kernel_headers.py @@ -106,6 +106,7 @@ def register_filter(gfx_level, name, offset, already_added): name.startswith('SQ_THREAD') or name.startswith('GRBM_STATUS') or name.startswith('CP_CP'))) or + name.startswith('GCVM_L2_PROTECTION_FAULT_STATUS') or # Add registers in the 0x9000 range (group == 0x9 and (name in ['TA_CS_BC_BASE_ADDR', 'GB_ADDR_CONFIG', 'SPI_CONFIG_CNTL'] or
