Module: Mesa Branch: main Commit: c945e0777d4e0db54ab81adbb7d7ef41adee7432 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c945e0777d4e0db54ab81adbb7d7ef41adee7432
Author: Tapani Pälli <[email protected]> Date: Thu Aug 31 10:48:26 2023 +0300 anv: add required PC for Wa_14014966230 Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25671> --- src/intel/vulkan/genX_cmd_buffer.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 7007b30d5cf..5dc62e8fb04 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -2853,6 +2853,19 @@ genX(batch_emit_pipe_control_write)(struct anv_batch *batch, { /* XXX - insert all workarounds and GFX specific things below. */ + /* Wa_14014966230: For COMPUTE Workload - Any PIPE_CONTROL command with + * POST_SYNC Operation Enabled MUST be preceded by a PIPE_CONTROL + * with CS_STALL Bit set (with No POST_SYNC ENABLED) + */ + if (intel_device_info_is_adln(devinfo) && + current_pipeline == GPGPU && + post_sync_op != NoWrite) { + anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe) { + pipe.CommandStreamerStallEnable = true; + anv_debug_dump_pc(pipe, "Wa_14014966230"); + }; + } + #if INTEL_NEEDS_WA_1409600907 /* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must * be set with any PIPE_CONTROL with Depth Flush Enable bit set.
