URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd674bf6289bc2b7a847401ef13b3a854479e99a
Author: Alejandro Piñeiro <[email protected]>
Date: Wed Oct 4 13:55:35 2023 +0200
doc/features: update after last v3d changes
V3D v71 supports new hw features, like 8 draw buffers.
As we are here, we also update some features that have been working
for some time now, even on v41.
Reviewed-by: Juan A. Suarez <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b9aaf25a00db63f3e2ae6ec047e23f54277f90f
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jun 21 10:29:07 2023 +0200
v3dv: expose scalarBlockLayout on V3D 7.x
This version of V3D doesn't have the restriction that vector accesses
must not cross 16-byte boundaries.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dff60b9ee5c310b69816233fccc731e2d6f42216
Author: Iago Toral Quiroga <[email protected]>
Date: Wed May 31 10:38:59 2023 +0200
v3dv: expose depthClamp in V3D 7.x
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2212ee82b733ab5f22a5770023ae593d0a331fb3
Author: Iago Toral Quiroga <[email protected]>
Date: Wed May 31 09:23:51 2023 +0200
v3dv: expose fullDrawIndexUint32 in V3D 7.x
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7999326f074dd2b9d4263bb39b74bacd32861a65
Author: Juan A. Suarez Romero <[email protected]>
Date: Mon Mar 20 16:48:51 2023 +0100
broadcom/simulator: add per-hw version calls
Add a wrapper to allow calling the right simulator function based on
the hardware under simulation.
Signed-off-by: Juan A. Suarez Romero <[email protected]>
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=314c8965a6ec70cdd896066920df763e0b8f9ca5
Author: Juan A. Suarez Romero <[email protected]>
Date: Wed Feb 22 09:43:40 2023 +0100
broadcom: add performance counters for V3D 7.x
Some of the counters need to be defined correctly.
v2: Remove references to extended performance counters. The hw does
not support them.
Signed-off-by: Juan A. Suarez Romero <[email protected]>
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d25aec0d386bee7f628e336c9b5939011bb7edc3
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Mar 9 19:05:19 2023 +0100
v3d,v3dv: fix compute for V3D 7.1.6+
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a698888031d3d59e1b25386bd78f6e59182723f
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Feb 8 09:04:02 2023 +0100
v3d,v3dv: fix depth bias for v3d 7.x
In v3d 7.x we don't need to scale up depth bias for D16 buffers.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd8afef9f134b6c31bfde9b077f3134f0d42c4cc
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Feb 8 08:41:12 2023 +0100
v3dv: fix color write mask for v3d 7.x
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=147112cfb17d38ca248843727e3b252db0593d98
Author: Iago Toral Quiroga <[email protected]>
Date: Tue May 16 00:38:40 2023 +0200
v3dv: use new texture shader state rb_swap and reverse fields in v3d 7.x
In v3d 4.x we handle formats that are reversed or R/B swapped by
applying a format swizzle. This doesn't work on border colors though,
and for that there is a specific bit to reverse the border color in
the texture shader state.
In v3d 7.x we have new reverse and swap R/B bits and we no longer have
a bit to reverse the border color because the new reverse bit applies
to border texels too. Because of this, we absolutely need to use these
new bits in order to get correct border colors in all cases with these
formats.
When we enable the reverse and/or swap R/B bits, we are effectively
applying the format swizzle through them, so in these cases we need to
make sure the swizzle we program in the texture shader state is the
view swizzle provided by the API and not the composition of the format
swizzle with the view swizzle like we do in 4.x for all formats. The
same applies to custom border colors: we must not apply the format
swizzle to them for formats that are reversed or R/B swapped, because
again, this format swizzle is already applied through these new bits.
While we are doing this, we also fully adopt the texture shader state
spec from v3d 7.1.5 for v3d 7.x instead of using a description from
7.1.2 which is incompatible and required the driver to manually pack
some of the bits.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6fe85136ef49dcaeb571a2b8b129c4b1197e6d8f
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Dec 3 13:20:22 2021 +0100
v3d,v3dv: propagate NaNs bits in shader state records are reserved in v7.x
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5f0305804b79b6f1cdd48f760f5fa47a5c4569f
Author: Alejandro Piñeiro <[email protected]>
Date: Fri Nov 19 10:51:37 2021 +0100
v3dv: implement depthBounds support for v71
Just for for v71, as that feature is not supported by older hw.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb9d0797398e9b0621eb65f401dbc67a126423b9
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Nov 16 11:26:17 2021 +0100
v3d,v3dv: don't use max internal bpp for tile sizing in V3D 7.x
We can use the actual bpp of each color attachment to compute real
tile memory requirements, which may allow us to choose a larger tile
size configuration than in V3D 4.2 in certain scenarios.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e90d955087dfa6b7487940f58d3613ac4082894
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Nov 12 10:35:59 2021 +0100
v3d,v3dv: support up to 8 render targets in v7.1+
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=904519d245ea6ce44dcd86459f36d749cb0d722e
Author: Iago Toral Quiroga <[email protected]>
Date: Tue May 16 00:28:27 2023 +0200
v3d/v3dv: fix texture state array stride packing for V3D 7.1.5
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=30920c5de46fabaea4c5a8a1bd2726e3c29b0f08
Author: Alejandro Piñeiro <[email protected]>
Date: Wed Oct 27 02:03:10 2021 +0200
v3d: add support for TFU blit in v71
TFU has changed on v71, specially on which registers to use, so that
means that support code change across versions. So as part of this
commit TFU copying is moved to a v3dx file.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e54fbc197c95ac133610385959080d474fb75dc3
Author: Alejandro Piñeiro <[email protected]>
Date: Fri Oct 22 14:26:29 2021 +0200
v3d: handle Z clipping in v71
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6eb063c66e68e94a1244501e660205084347f805
Author: Alejandro Piñeiro <[email protected]>
Date: Fri Oct 22 13:41:09 2021 +0200
v3d: don't convert floating point border colors in v71
The TMU does this for us now.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=610799cb4f8b9074b91a2e6b17b4931349272dd3
Author: Alejandro Piñeiro <[email protected]>
Date: Fri Oct 22 12:17:45 2021 +0200
v3d: GFX-1461 does not affect V3D 7.x
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e743d41756101cce7cda469895f76d60de8506a7
Author: Alejandro Piñeiro <[email protected]>
Date: Fri Oct 22 11:40:49 2021 +0200
v3d: setup render pass color clears for any format bpp in v71
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9be4d4def6f801e08c1007ae9d3ea95c972d8488
Author: Alejandro Piñeiro <[email protected]>
Date: Fri Oct 22 10:54:24 2021 +0200
v3d: handle new TEXTURE_SHADER_STATE v71 YCbCr fields
There are some new fields for YCbCr with pointers for the various
planes in multi-planar formats. These need to match the base address
pointer in the texture state, or the hardware will assume this is a
multi-planar texture.
Notice we don't use an address type for these fields in the XML
description. This is because the addresses are 64-bit aligned (even
though the PRM doesn't say it) which means the 6 LSB bits are
implicitly 0, but the fields are encoded before the 6th bit of their
starting byte, so we can't use the usual trick we do with address
types where the first 6 bits in the byte are implicitly overwritten by
other fields and we have to encode this manually as a uint field. This
would mean that if we had an actual BO we would also need to add it
manually to the job's list, but since we don't have one, we don't have
to do anything about it.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=80923c889a030c0afa37e2f6cd718793ce56cac2
Author: Alejandro Piñeiro <[email protected]>
Date: Thu Oct 21 23:21:02 2021 +0200
v3d: handle new texture state transfer functions in v71
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b09f9156661b4d4bec4e5494f3c106b0aac1f5f7
Author: Alejandro Piñeiro <[email protected]>
Date: Thu Oct 21 13:46:11 2021 +0200
v3d/uniforms: update VIEWPORT_X/Y_SCALE uniforms for v71
As the packet CLIPPER_XY scaling, this needs to be computed on 1/64ths
of pixel, instead of 1/256ths of pixels.
As this is the usual values that we get from macros, we add manually a
v42 and v71 macro, and define a new helper to get those.
Those granularity values are the same for Vulkan and OpenGL, so
perhaps we should move them to a common place.
As with v3dv, V3D_X macro name is somewhat confusing. It is
specifically created to ask for define values that depends on the
version. But I also felt that V3D_DEFINE_X was too long.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2908b2782ae900e9aef8c62686c035ece7764411
Author: Alejandro Piñeiro <[email protected]>
Date: Thu Oct 21 13:37:46 2021 +0200
v3d: default vertex attributes values are not needed for v71
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b833243348089c4e20d151c27ab35fbc028d3820
Author: Alejandro Piñeiro <[email protected]>
Date: Thu Oct 21 13:19:49 2021 +0200
v3d: no specific separate_segments flag for V3D 7.1
On V3D 7.1 there is not a flag on the Shader State Record to specify
if we are using shared or separate segments. This is done by setting
the vpm input size to 0 (so we need to ensure that the output would be
the max needed for input/output).
We were already doing the latter on the prog_data_vs, so we just need
to use those values, instead of assigning default values.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=12e968046c1acbcb0d9a31ec411fa27b13b76406
Author: Alejandro Piñeiro <[email protected]>
Date: Thu Oct 21 13:14:32 2021 +0200
v3d: emit CLIPPER_XY_SCALING for v71
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6561f58b0d4863534e73bf3f3080d504d92d3b75
Author: Alejandro Piñeiro <[email protected]>
Date: Thu Oct 21 13:09:03 2021 +0200
v3d: just don't fill up early-z fields for CFG_BITS for v71
v71 doesn't include early_z_enable/early_z_updates_enable. They are
configured with packet 121.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=22817f4f89b2afb5412fe46ee3a1d00608e5b402
Author: Alejandro Piñeiro <[email protected]>
Date: Thu Oct 21 01:47:29 2021 +0200
v3d: emit CLEAR_RENDER_TARGETS for v71
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=68b3b7c8510c166a570940c1fc47b0abea6177ea
Author: Alejandro Piñeiro <[email protected]>
Date: Wed Oct 20 15:12:15 2021 +0200
v3d: TILE_RENDERING_MODE_CFG_RENDER_TARGET_PART1
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=da11be4bdf21d276a82aff68234fa68dededd31d
Author: Alejandro Piñeiro <[email protected]>
Date: Wed Oct 20 14:31:10 2021 +0200
v3d: emit TILE_BINNING_MODE_CFG and TILE_RENDERING_MODE_CFG_COMMON for v71
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4dfe17a7626cc8fa18c50829dcd35f7bae731b77
Author: Alejandro Piñeiro <[email protected]>
Date: Tue May 23 23:32:37 2023 +0200
v3d: add v71 hw generation
Starting point for v71 version inclusion:
* Adds as one of the versions to be compiled on meson
* Updated the v3d_X and v3dX macros to include version 71
* Update the code enough to get it building when using v71.
Any real v71 support will be implemented on following commits.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48383668a7c53f3edda9ab266a0ef00ca20fbf95
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Feb 14 10:09:53 2023 +0100
v3dv: fix depth clipping then Z scale is too small in V3D 7.x
When the Z scale is too small guardband clipping may not clip
correctly, so disable it, which is a new option in V3D 7.x.
This fixes this test in V3D 7.x without needing any workarounds:
dEQP-VK.draw.renderpass.inverted_depth_ranges.nodepthclamp_deltazero
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=662d6e296e44a4be499a10b6046bc67dd98050a3
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Oct 20 11:22:11 2021 +0200
v3dv: make v3dv_viewport_compute_xform depend on the V3D version
For 4.x we have a workaround for too small Z scale values that is not
required for V3D 7.x.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=146ceadcf45db7d2e6434ccc816f133da8dcd81f
Author: Alejandro Piñeiro <[email protected]>
Date: Wed Nov 17 11:33:59 2021 +0100
v3dv: add support for TFU jobs in v71
This includes update the simulator.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f2704a28de69b44f5d5f9128f252f8a45929cde
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Oct 15 13:06:31 2021 +0200
v3dv: handle Z clipping in v71
Fixes the following tests:
dEQP-VK.clipping.clip_volume.*
dEQP-VK.draw.inverted_depth_ranges.nodepthclamp_* (except deltazero)
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=acd99e08b4fcec260d03e05ee2a6b1a9433180fa
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Oct 7 12:43:49 2021 +0200
v3dv: don't convert floating point border colors in v71
The TMU does this for us now.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=452421dfe56f35a909a7231008f00b29922a5c44
Author: Alejandro Piñeiro <[email protected]>
Date: Fri Oct 1 15:18:38 2021 +0200
v3dv: no specific separate_segments flag for V3D 7.1
On V3D 7.1 there is not a flag on the Shader State Record to specify
if we are using shared or separate segments. This is done by setting
the vpm input size to 0 (so we need to ensure that the output would be
the max needed for input/output).
We were already doing the latter on the prog_data_vs, so we just need
to use those values, instead of assigning default values.
As we are here, we also add some comments on the compiler part.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef60f6db0d62137dc0adf924f66e5aea72ef938c
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Sep 29 09:07:28 2021 +0200
v3dv: handle RTs with no color targets in v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f4fa1c8586434b50b50c3d67422571bed4ce53ab
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Sep 29 08:22:59 2021 +0200
v3dv: handle early Z/S clears for v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c191d1103127703c8d1dac6ce3d0b785c81ea44
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Sep 28 08:59:08 2021 +0200
broadcom/compiler: update thread end restrictions validation for v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7b16f91e115092c3de31bb153a024fc60a8d3cf
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Sep 28 08:31:04 2021 +0200
v3dv: GFX-1461 does not affect V3D 7.x
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=84ca72ace2616b1eaf3c9b0a74bebebee47dfc71
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Sep 28 08:23:48 2021 +0200
v3dv: handle render pass global clear for v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=76a019f8cc0c9b12bed665a5696ae034b79c7792
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Sep 28 08:14:11 2021 +0200
v3dv: implement noop job for v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ad415c0e6fd95806c5e860e4f843bca7af86388
Author: Iago Toral Quiroga <[email protected]>
Date: Mon Oct 25 01:38:31 2021 +0200
v3dv: handle new texture state transfer functions in v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe6594c4c114c91f0bdf0b96c28349e6f2a1e18d
Author: Iago Toral Quiroga <[email protected]>
Date: Mon Oct 25 01:37:12 2021 +0200
v3dv: fix up texture shader state for v71
There are some new fields for YCbCr with pointers for the various
planes in multi-planar formats. These need to match the base address
pointer in the texture state, or the hardware will assume this is a
multi-planar texture.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f514ad5dd2a600d0d759f2bab1c8ac5bbaba798f
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Sep 22 12:04:21 2021 +0200
v3dv: setup TLB clear color for meta operations in v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5e3322d9358386793197b9c723d3be0968a5ef7
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Sep 22 12:03:58 2021 +0200
v3dv: setup render pass color clears for any format bpp in v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c92a758ccbb5cbfeca2dfbe2badef894e5b6dfc
Author: Alejandro Piñeiro <[email protected]>
Date: Wed Jul 28 13:45:52 2021 +0200
v3dv/pipeline: handle GL_SHADER_STATE_RECORD changed size on v71
It is likely that we would need more changes, as this packet changed,
but this is enough to get basic tests running. Any additional support
will be handled with new commits.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5750926d0e583b0503eec03f686fe679ccd80701
Author: Alejandro Piñeiro <[email protected]>
Date: Wed Jul 28 12:05:26 2021 +0200
v3dv/pipeline: default vertex attributes values are not needed for v71
There are not part of the shader state record.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=53773f3ea7a2f0e9c5bfd6ac5a5bd2167a1eccc5
Author: Alejandro Piñeiro <[email protected]>
Date: Wed Jul 28 12:01:38 2021 +0200
v3dv: default vertex attribute values are gen dependant
Content, structure and size would depend on the generation. Even if it
is needed at all.
So let's move it to the v3dvx files.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0abf7c14077b020ef525d29d0b5777929dcf952e
Author: Alejandro Piñeiro <[email protected]>
Date: Tue Jul 27 14:02:30 2021 +0200
v3dv/cmd_buffer: just don't fill up early-z fields for CFG_BITS for v71
For v71 early_z_enable/early_z_updates_enable is configured with
packet 121.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a822ba3e64003f7c5e095fafc54f6692ad261fd
Author: Alejandro Piñeiro <[email protected]>
Date: Tue Sep 14 10:08:19 2021 +0200
v3dv/uniforms: update VIEWPORT_X/Y_SCALE uniforms for v71
As the packet CLIPPER_XY scaling, this needs to be computed on 1/64ths
of pixel, instead of 1/256ths of pixels.
As this is the usual values that we get from macros, we add manually a
v42 and v71 macro, and define a new helper (V3DV_X) to get the value
for the current hw version.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0fdd9ea9bcbca30bccce492d2765bc5ef09d469b
Author: Alejandro Piñeiro <[email protected]>
Date: Sun Sep 19 23:37:32 2021 +0200
v3dv/cmd_buffer: emit CLIPPER_XY_SCALING for v71
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2eed3fff6e3017446eb3b4488d9c3db4e9ea33c
Author: Alejandro Piñeiro <[email protected]>
Date: Mon Jul 26 15:08:11 2021 +0200
v3dvx/cmd_buffer: emit CLEAR_RENDER_TARGETS for v71
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=33886d5f2657cb0ebf379de2d07919f91d7c2026
Author: Alejandro Piñeiro <[email protected]>
Date: Thu Jul 22 14:26:13 2021 +0200
v3dv/cmd_buffer: emit TILE_RENDERING_MODE_CFG_RENDER_TARGET_PART1 for v71
Signed-off-by: Alejandro Piñeiro <[email protected]>
Signed-off-by: Iago Toral Quiroga <[email protected]>
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5cc035a7505181c38b727817d58c7c36e6ff8a7e
Author: Alejandro Piñeiro <[email protected]>
Date: Tue Jul 20 14:00:44 2021 +0200
v3dv: emit TILE_BINNING_MODE_CFG and TILE_RENDERING_MODE_CFG_COMMON for v71
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f8d331188a9314fa310bdc1dec4122a3734d493
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Nov 10 07:54:35 2021 +0100
v3dv/device: handle new rpi5 device (bcm2712)
This includes both master and primary devices.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=15a0ad216a83fb6ebf4654e75e50e0c3e6c94b83
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Nov 10 10:06:50 2021 +0100
v3dv: expose V3D revision number in device name
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4606904215da86c91ff306a7b461a3796d775fa5
Author: Alejandro Piñeiro <[email protected]>
Date: Tue Jun 29 11:59:53 2021 +0200
v3dv/meson: add v71 hw generation
Starting point for v71 version inclusion.
This just adds it as one of the versions to be compiled (on meson),
updates the v3dX/v3dv_X macros, and update the code enough to get it
compiling when building using the two versions. For any packet not
available on v71 we just provide a generic asserted placeholder of
generation not supported.
Any real v71 support will be implemented on following commits.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f5a3391bbf8bb5f2bef047ddfcf08e6aa5f5794
Author: Iago Toral Quiroga <[email protected]>
Date: Mon May 15 10:02:10 2023 +0200
broadcom/compiler: only assign rf0 as last resort in V3D 7.x
So we can use it for ldunif(a) and avoid generating ldunif(a)rf which
can't be paired with conditional instructions.
shader-db (pi5):
total instructions in shared programs: 11357802 -> 11338883 (-0.17%)
instructions in affected programs: 7117889 -> 7098970 (-0.27%)
helped: 24264
HURT: 17574
Instructions are helped.
total uniforms in shared programs: 3857808 -> 3857815 (<.01%)
uniforms in affected programs: 92 -> 99 (7.61%)
helped: 0
HURT: 1
total max-temps in shared programs: 2230904 -> 2230199 (-0.03%)
max-temps in affected programs: 52309 -> 51604 (-1.35%)
helped: 1219
HURT: 725
Max-temps are helped.
total sfu-stalls in shared programs: 15021 -> 15236 (1.43%)
sfu-stalls in affected programs: 6848 -> 7063 (3.14%)
helped: 1866
HURT: 1704
Inconclusive result
total inst-and-stalls in shared programs: 11372823 -> 11354119 (-0.16%)
inst-and-stalls in affected programs: 7149177 -> 7130473 (-0.26%)
helped: 24315
HURT: 17561
Inst-and-stalls are helped.
total nops in shared programs: 273624 -> 273711 (0.03%)
nops in affected programs: 31562 -> 31649 (0.28%)
helped: 1619
HURT: 1854
Inconclusive result (value mean confidence interval includes 0).
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c8e4ee8ecbff817479c442b83c61fefeccf01f2c
Author: Iago Toral Quiroga <[email protected]>
Date: Tue May 2 10:17:47 2023 +0200
broadcom/compiler: don't assign registers to unused nodes/temps
In programs with a lot of unused temps, if we don't do this, we may
end up recycling previously used rfs more often, which can be
detrimental to instruction pairing.
total instructions in shared programs: 11464335 -> 11444136 (-0.18%)
instructions in affected programs: 8976743 -> 8956544 (-0.23%)
helped: 33196
HURT: 33778
Inconclusive result
total max-temps in shared programs: 2230150 -> 2229445 (-0.03%)
max-temps in affected programs: 86413 -> 85708 (-0.82%)
helped: 2217
HURT: 1523
Max-temps are helped.
total sfu-stalls in shared programs: 18077 -> 17104 (-5.38%)
sfu-stalls in affected programs: 8669 -> 7696 (-11.22%)
helped: 2657
HURT: 2182
Sfu-stalls are helped.
total inst-and-stalls in shared programs: 11482412 -> 11461240 (-0.18%)
inst-and-stalls in affected programs: 8995697 -> 8974525 (-0.24%)
helped: 33319
HURT: 33708
Inconclusive result
total nops in shared programs: 298140 -> 296185 (-0.66%)
nops in affected programs: 52805 -> 50850 (-3.70%)
helped: 3797
HURT: 2662
Inconclusive result
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce13aa4ee7d6251e8cfa928ebbd8b39a63e861c3
Author: Iago Toral Quiroga <[email protected]>
Date: Tue May 2 10:12:37 2023 +0200
broadcom/compiler: improve allocation for final program instructions
The last 3 instructions can't use specific registers so flag all the
nodes for temps used in the last program instructions and try to
avoid assigning any of these. This may help us avoid injecting nops
for the last thread switch instruction.
Because regisster allocation needs to happen before QPU scheduling
and instruction merging we can't tell exactly what the last 3
instructions will be, so we do this for a few more instructions than
just 3.
We only do this for fragment shaders because other shader stages
always end with VPM store instructions that take an small immediate
and therefore will never allow us to merge the final thread switch
earlier, so limiting allocation for these shaders will never improve
anything and might instead be detrimental.
total instructions in shared programs: 11471389 -> 11464335 (-0.06%)
instructions in affected programs: 582908 -> 575854 (-1.21%)
helped: 4669
HURT: 578
Instructions are helped.
total max-temps in shared programs: 2230497 -> 2230150 (-0.02%)
max-temps in affected programs: 5662 -> 5315 (-6.13%)
helped: 344
HURT: 44
Max-temps are helped.
total sfu-stalls in shared programs: 18068 -> 18077 (0.05%)
sfu-stalls in affected programs: 264 -> 273 (3.41%)
helped: 37
HURT: 48
Inconclusive result (value mean confidence interval includes 0).
total inst-and-stalls in shared programs: 11489457 -> 11482412 (-0.06%)
inst-and-stalls in affected programs: 585180 -> 578135 (-1.20%)
helped: 4659
HURT: 588
Inst-and-stalls are helped.
total nops in shared programs: 301738 -> 298140 (-1.19%)
nops in affected programs: 14680 -> 11082 (-24.51%)
helped: 3252
HURT: 108
Nops are helped.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=818fc41e7e48e4353ed368c6f61d0f70e84a48c5
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Apr 18 08:50:13 2023 +0200
broadcom/compiler: don't allocate spill base to rf0 in V3D 7.x
Otherwise it can be stomped by instructions doing implicit rf0 writes.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc6ed98aae965687ee297a0907f276717380d04d
Author: Alejandro Piñeiro <[email protected]>
Date: Fri Nov 26 01:24:12 2021 +0100
broadcom/qpu: new packing/conversion v71 instructions
This commits adds the qpu definitions for several new v71
instructions.
Packing:
* vpack does a 2x32 to 2x16 bit integer pack
* v8pack: Pack 2 x 2x16 bit integers into 4x8 bits
* v10pack packs parts of 2 2x16 bit integer into r10g10b10a2.
* v11fpack packs parts of 2 2x16 bit float into r11g11b10 rounding
to nearest
Conversion to unorm/snorm:
* vftounorm8/vftosnorm8: converts from 2x16-bit floating point
to 2x8 bit unorm/snorm.
* ftounorm16/ftosnorm16: converts floating point to 16-bit
unorm/snorm
* vftounorm10lo: Convert 2x16-bit floating point to 2x10-bit unorm
* vftounorm10hi: Convert 2x16-bit floating point to one 2-bit and one
10-bit unorm
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=84c912c1d4638b4871dcf11facc6a2c91630c974
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Nov 9 11:34:59 2021 +0100
broadcom/compiler: fix up copy propagation for v71
Update rules for unsafe copy propagations to match v7.x.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e85be415a0b3fbf04dde28d9ac2d47054b0ed21
Author: Iago Toral Quiroga <[email protected]>
Date: Mon Nov 29 13:23:11 2021 +0100
broadcom/compiler: lift restriction on vpmwt in last instruction for V3D 7.x
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=277460178077248f696183a55bbb4e5ea723fd78
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Nov 25 13:00:34 2021 +0100
broadcom/compiler: validate restrictions after TLB Z write
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4285d7f2a076a5b2e8c536e7c88ed37b6ee142a
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Nov 26 10:37:05 2021 +0100
broadcom/compiler: start allocating from RF 4 in V7.x
In V3D 4.x we start at RF3 so that we allocate RF0-2 only if there
aren't any other RFs available. This is useful with small shaders to
ensure that our TLB writes don't use these registers because these are
the last instructions we emit in fragment shaders and the last
instructions in a program can't write to these registers, so if we do,
we need to emit NOPs.
In V3D 7.x the registers affected by this restriction are RF2-3, so we
choose to start at RF4.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b39bb35c5ce383ec047f474e69e80c8275bfece
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Nov 25 08:31:02 2021 +0100
broadcom/compiler: lift restriction for branch + msfign after setmsf for
v7.x
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e9b405aa71cd1d29c9dc57f9a4385630844e03b
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Nov 23 10:04:49 2021 +0100
broadcom/compiler: update ldvary thread switch delay slot restriction for
v7.x
In V3D 7.x we don't have accumulators which would not survive a thread
switch, so the only restriction is that ldvary can't be placed in the
second delay slot of a thread switch.
shader-db results for UnrealEngine4 shaders:
total instructions in shared programs: 446458 -> 446401 (-0.01%)
instructions in affected programs: 13492 -> 13435 (-0.42%)
helped: 58
HURT: 3
Instructions are helped.
total nops in shared programs: 19571 -> 19541 (-0.15%)
nops in affected programs: 161 -> 131 (-18.63%)
helped: 30
HURT: 0
Nops are helped.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=526c1889e5d591da5c71caca5699f51e1f129be4
Author: Iago Toral Quiroga <[email protected]>
Date: Mon Nov 22 12:56:03 2021 +0100
broadcom/compiler: update thread end restrictions for v7.x
In 4.x it is not allowed to write to the register file in the last 3
instructions, but in 7.x we only have this restriction in the thread
end instruction itself, and only if the write comes from the ALU
ports.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ced83e7803dc305eeda03f787f042afb8608f18a
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Nov 3 10:34:19 2021 +0100
broadcom/compiler: implement small immediates for v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4d30600a4c31607e491d79931e3e29782138776
Author: Iago Toral Quiroga <[email protected]>
Date: Mon Oct 25 09:38:57 2021 +0200
broadcom/compiler: convert mul to add when needed to allow merge
V3D 7.x added 'mov' opcodes to the ADD alu, so now it is possible to
move these to the ADD alu to facilitate merging them with other MUL
instructions.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cbedf1468743f44b02fa9c2e3d5077cab6121a5e
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Oct 29 13:00:56 2021 +0200
broadcom/compiler: don't assign rf0 to temps that conflict with ldvary
ldvary writes to rf0 implicitly, so we don't want to allocate rf0 to
any temps that are live across ldvary's rf0 live ranges.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a36a618d74a4dfca19d8ad2424722edcd77b0c8
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Oct 28 14:13:29 2021 +0200
broadcom/compiler: try to use ldunif(a) instead of ldunif(a)rf in v71
The rf variants need to encode the destination in the cond bits, which
prevents these to be merged with any other instruction that need them.
In 4.x, ldunif(a) write to r5 which is a special register that only
ldunif(a) and ldvary can write so we have a special register class for
it and only allow it for them. Then when we need to choose a register
for a node, if this register is available we always use it.
In 7.x these instructions write to rf0, which can be used by any
instruction, so instead of restricting rf0, we track the temps that
are used as ldunif(a) destinations and use that information to favor
rf0 for them.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8a25bdb0717efa16f65bf019b692aec3e2973e4
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Oct 27 11:35:12 2021 +0200
broadcom/compiler: enable ldvary pipelining on v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8014be2b07585b8c38bd37725213c093cb151ae
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Oct 6 13:58:27 2021 +0200
broadcom/compiler: handle rf0 flops storage restriction in v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=852274d00ab027fc6ce3ffbe71de0b3966c6d584
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Oct 26 08:37:54 2021 +0200
broadcom/qpu: add packing for fmov on ADD alu
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1281d857fc5b4f5fb2bd7e1104332138a1731e5
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Oct 26 11:43:02 2021 +0200
broadcom/compiler: update peripheral access restrictions for v71
In V3D 4.x only a couple of simultaneous accesses where allowed, but
V3D 7.x is a bit more flexible, so rather than trying to check for all
the allowed combinations it is easier to check if we are one of the
disallows.
Shader-db (pi5):
total instructions in shared programs: 11338883 -> 11307386 (-0.28%)
instructions in affected programs: 2727201 -> 2695704 (-1.15%)
helped: 12555
HURT: 289
Instructions are helped.
total max-temps in shared programs: 2230199 -> 2229260 (-0.04%)
max-temps in affected programs: 20508 -> 19569 (-4.58%)
helped: 608
HURT: 4
Max-temps are helped.
total sfu-stalls in shared programs: 15236 -> 15293 (0.37%)
sfu-stalls in affected programs: 148 -> 205 (38.51%)
helped: 38
HURT: 64
Inconclusive result (%-change mean confidence interval includes 0).
total inst-and-stalls in shared programs: 11354119 -> 11322679 (-0.28%)
inst-and-stalls in affected programs: 2732262 -> 2700822 (-1.15%)
helped: 12550
HURT: 304
Inst-and-stalls are helped.
total nops in shared programs: 273711 -> 274095 (0.14%)
nops in affected programs: 9626 -> 10010 (3.99%)
helped: 186
HURT: 397
Nops are HURT.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce66c9aead9e26cb29b631e0ab317c7630719a6a
Author: Alejandro Piñeiro <[email protected]>
Date: Tue Oct 19 23:52:30 2021 +0200
broadcom/compiler: update payload registers handling when computing live
intervals
As for v71 the payload registers are not the same. Specifically now
rf3 is used as payload register, so this is needed to avoid rf3 being
selected as a instruction dst by the register allocator, overwriting
the payload value that could be still used.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d72e57fe30f6e646e58394dc9d9a7431028822d7
Author: Alejandro Piñeiro <[email protected]>
Date: Tue Oct 19 11:51:32 2021 +0200
broadcom/compiler: update ldunif/ldvary comment for v71
For v42 and below ldunif/ldvary write both on r5, but with a different
delay, so we need to take that into account when scheduling both.
For v71 the register used is rf0, but the behaviour is the same. So
the scheduling code can be the same, but the comment needs update.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3aba3f3528188b1e8a2e9d232d16dc43d7d2542
Author: Alejandro Piñeiro <[email protected]>
Date: Tue Oct 19 11:16:43 2021 +0200
broadcom/compiler: update one TMUWT restriction for v71
TMUWT not allowed in the final instruction restriction doesn't apply
for v71.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9fcd5d7868ad878ff23f7a201f303d39a0939b7
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Oct 14 14:16:40 2021 +0200
broadcom/compiler: v71 isn't affected by double-rounding of viewport X,Y
coords
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c7224b81f96f897616deca50bbc36744ea04110
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Oct 8 15:10:24 2021 +0200
broadcom/compiler: generalize check for shaders using pixel center W
V3D 4.x has pixel center W in rf0 and V3D 7.x has it in rf3. We already
account for this when we setup the c->payload_w, so use that.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff86147f91edba89117c90114c446de29a0a5b2f
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Oct 6 12:01:10 2021 +0200
broadcom/qpu: fail packing on unhandled mul pack/unpack
We are doing this for the ADD alu already and it may be helpful to
identify cases where we have QPU code with pack/unpack modifiers on
MUL opcodes that we then are not packing into the actual QPU
instructions.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5fc2b565a4e6e7bfe9e5e18922c2de5e00c63cc2
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Oct 6 09:27:43 2021 +0200
broadcom/qpu: add MOV integer packing/unpacking variants
These are new in v71 and cover MOV on both the ADD and the MUL alus.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4e0c9bac4273c58c187a078122129bde5e74411
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Sep 30 13:22:48 2021 +0200
broadcom/compiler: allow instruction merges in v71
In v3d 4.x there were restrictions based on the number of raddrs used
by the combined instructions, but we don't have these restrictions in
v3d 7.x.
It should be noted that while there are no restrictions on the number
of raddrs addressed, a QPU instruction can only address a single small
immediate, so we should be careful about that when we add support for
small immediates.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=28631a5550ac2b42fe205fe85ae215ef040f8633
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Oct 22 13:39:48 2021 +0200
broadcom/compiler: don't schedule rf0 writes right after ldvary
ldvary writes rf0 implicitly on the next cycle so they would clash.
This case is not handled correctly by our normal dependency tracking,
which doesn't know anything about delayed writes from instructions
and thinks the rf0 write happens on the same cycle ldvary is emitted.
Fixes (v71):
dEQP-VK.glsl.conversions.matrix_to_matrix.mat2x3_to_mat4x2_fragment
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=42b70f624b2a4ec9b17a745235a3ef601dd3816f
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Sep 28 13:37:28 2021 +0200
broadcom/compiler: CS payload registers have changed in v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b15df963ef142bcf4b075253be3d82d3272a60c
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Sep 29 12:14:04 2021 +0200
broadcom/compiler: don't assign rf0 to temps across implicit rf0 writes
In platforms that don't have accumulators and have implicit writes to
the register file we need to be careful and avoid assigning a physical
register to a temp that lives across an implicit write to that same
physical register.
For now, we have the case of implicit writes to rf0 from various
signals, but it should be easy to extend this to include additional
registers if needed.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=03594b3dcaf31226d3417ecf2829c7cabad4d54e
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Sep 29 12:10:31 2021 +0200
broadcom/compiler: only handle accumulator classes if present
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1548b18d39c2ea6d3204abebf330b305fb46bc3
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Sep 29 12:03:50 2021 +0200
broadcom/compiler: rename vir_writes_rX to vir_writes_rX_implicitly
Since that represents more accurately what they check..
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=20b37b273f86d6eff4a99b30de90c914d6cc3c08
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Sep 29 11:54:18 2021 +0200
broadcom/compiler: make vir_write_rX return false on platforms without
accums
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=310dec3ec94922f10801cbbf039d9047358cc0c5
Author: Alejandro Piñeiro <[email protected]>
Date: Tue Sep 28 01:17:08 2021 +0200
broadcom/qpu: implement switch rules for fmin/fmax fadd/faddnf for v71
They use the same opcodes, and switch between one and the other based
on raddr.
Note that the rule includes also if small_imm_a/b are used. That is
still not in place so that part is hardcoded. Would be updated later
when small immediates support for v71 gets implemented.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ef31ba460f563b22d29abf203e31b83d8a6cf2a
Author: Iago Toral Quiroga <[email protected]>
Date: Mon Oct 4 13:07:35 2021 +0200
broadcom/qpu: fix packing/unpacking of fmov variants for v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9b44ae0c82accffbbd3bf9d39d159dfc6446839
Author: Iago Toral Quiroga <[email protected]>
Date: Mon Sep 27 13:26:04 2021 +0200
broadcom/qpu: add new ADD opcodes for FMOV/MOV in v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=caf28e568120b06a749bfe9244959f47d542c4fa
Author: Iago Toral Quiroga <[email protected]>
Date: Mon Sep 27 11:49:24 2021 +0200
broadcom/compiler: prevent rf2-3 usage in thread end delay slots for v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=28bb1b3ff6f7bafb685df07a818d963a50fd48c5
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Oct 6 13:58:00 2021 +0200
broadcom/compiler: add a v3d71_qpu_writes_waddr_explicitly helper
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=572fba0bf445ab2f19fc091f1de1b3f2f156504e
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Sep 23 11:44:59 2021 +0200
broadcom/compiler: implement read stall check for v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e26d2c1568c116f7c4a70e402ba9bfd41d83d76
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Sep 23 11:19:58 2021 +0200
broadcom/compiler: implement "reads/writes too soon" checks for v71
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=083d082d8edc147ab0f5a9bdcff62f8b3b0e824a
Author: Alejandro Piñeiro <[email protected]>
Date: Thu Sep 16 00:49:25 2021 +0200
broadcom/compiler: update register classes to not include accumulators on
v71
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d12eb68d3a9e6a2869f181c5ac3064256ed2787c
Author: Alejandro Piñeiro <[email protected]>
Date: Wed Sep 15 11:12:59 2021 +0200
broadcom/qpu_schedule: update write deps for v71
We just need to add a write dep if rf0 is written implicitly.
Note that we don't need to check if we have accumulators when checking
for r3/r4/r5, as v3d_qpu_writes_rX would return false for hw version
that doesn't have accumulators.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a035af931a291c6c29d30c94b2134eda6d0584b
Author: Alejandro Piñeiro <[email protected]>
Date: Wed Sep 15 01:14:15 2021 +0200
broadcom/compiler: payload_w is loaded on rf3 for v71
And in general rf0 is now used for other needs.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=edfc36817a97ad1905c2028e970369e136daf300
Author: Alejandro Piñeiro <[email protected]>
Date: Tue Sep 14 10:42:55 2021 +0200
broadcom/compiler: add support for varyings on nir to vir generation for v71
Needs update as v71 doesn't have accumulators anymore, and ldvary uses
now rf0 to return the value.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=68526423fbfbeff033e7a3846c3a1f95b3e725ab
Author: Alejandro Piñeiro <[email protected]>
Date: Wed Sep 15 10:55:49 2021 +0200
broadcom/qpu: return false on qpu_writes_accumulatorXX helpers for v71
As for v71 doesn't have accumulators (devinfo->has_accumulators set to
false), those methods would always return false.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7b15c2b42e5bc0125ad26192fac09ef46e937c6
Author: Alejandro Piñeiro <[email protected]>
Date: Fri Sep 10 01:20:44 2021 +0200
broadcom/qpu: update disasm_raddr for v71
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a766cc3a5aa2fac85a80cfe8976d9f7dfca4ecd7
Author: Alejandro Piñeiro <[email protected]>
Date: Thu Sep 9 23:59:28 2021 +0200
broadcom/qpu_schedule: add process_raddr_deps
On v71 we don't have muxes, but more raddr. Adding a equivalent add
deps function.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dad6917d5eb17c59e21998fb4698685c591b34a4
Author: Alejandro Piñeiro <[email protected]>
Date: Thu Sep 9 01:18:54 2021 +0200
broadcom/compiler: update vir_to_qpu::set_src for v71
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=136d934c80a3f84a02cb2c1ba04dc3724f1214cd
Author: Alejandro Piñeiro <[email protected]>
Date: Thu Sep 9 00:28:53 2021 +0200
broadcom/vir: implement is_no_op_mov for v71
Did some refactoring/splitting.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d00f7ef23e25933c7fb00a19d9d88cdbd4d9aaba
Author: Alejandro Piñeiro <[email protected]>
Date: Fri Sep 17 01:07:06 2021 +0200
broadcom/compiler: don't favor/select accum registers for hw not supporting
it
Note that what we do is to just return false on the favor/select accum
methods. We could just avoid to call them, but as the select is called
more than once, it is just easier this way.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1260b202becce6164675eed0f86e873243083d0e
Author: Alejandro Piñeiro <[email protected]>
Date: Mon Aug 23 02:18:43 2021 +0200
broadcom/compiler: phys index depends on hw version
For 7.1 there are not accumulators. So we replace the macro with a
function call.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=63d633ca7af4000e5001aca639831c0302a13e4d
Author: Iago Toral Quiroga <[email protected]>
Date: Sun Jan 29 00:27:11 2023 +0100
broadcom/compiler: update node/temp translation for v71
As the offset applied needs to take into account if we have
accumulators or not.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b20208f03f69bab3dd22d28344cc3a01c321d28
Author: Alejandro Piñeiro <[email protected]>
Date: Sat Aug 7 02:20:39 2021 +0200
broadcom/qpu: add pack/unpack support for v71
Note that we provide new v71 alu pack/unpack methods. As there are a
lot that it is equivalent, initially we tried to use existing methods
as template and add version checks on the existing methods. At some
early point that become just really unreadable, so it become better to
just provide new methods, even if v42 and v71 methods have a really
similar structure.
Note that we have splitted the op tables, and created a two (add/mul)
for v71. As the description struct include versioning info, we could
have just used one table. But, specially with the add table, there are
a lot of differences with v71. So it is slightly tidier this
way. Also, taking into account that we do a linear search on the
tables, this can be even justified by performance.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c07eb1bae5ef45a33a939f1ab2f9a6775627925c
Author: Alejandro Piñeiro <[email protected]>
Date: Wed Sep 15 10:56:43 2021 +0200
broadcom/qpu: add qpu_writes_rf0_implicitly helper
On v71 rf0 replaces r5 as the register that gets updated implicitly
with uniform loads, and gets the C coefficient with ldvary. This
helper return if rf0 gets implicitly updated.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e42b9ff47476c4caffae03bc0dc4d0fb5f0fc98
Author: Alejandro Piñeiro <[email protected]>
Date: Fri Sep 17 01:04:31 2021 +0200
broadcom/commmon: add has_accumulators field on v3d_device_info
Even if we can just check for the version on the code, checking for
this field makes several places more readable. So for example, on the
register allocate code we doesn't assign an accumulator because we
don't have accumulators on that hw, instead of because hw version is a
given one.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef75d07b87be468c0ae11781e10f1f454d82f216
Author: Alejandro Piñeiro <[email protected]>
Date: Thu Aug 12 02:24:02 2021 +0200
broadcom/qpu: defining shift/mask for raddr_c/d
On V3D 7.x it replaces mul_a/b and add_a/b
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5c4634c9e4a9472de2e150c0388723b671c2af5
Author: Alejandro Piñeiro <[email protected]>
Date: Fri Aug 6 01:33:32 2021 +0200
broadcom/qpu: add raddr on v3d_qpu_input
On V3D 7.x mux are not used, and raddr_a/b/c/d are used instead
This is not perfect, as for v71, the raddr_a/b defined at qpu_instr
became superfluous. But the alternative would be to define two
different structs, or even having them defined based on version
ifdefs, so this is a reasonable compromise.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=347065525f2d3db68e90c850e5c619ff4bd81e23
Author: Alejandro Piñeiro <[email protected]>
Date: Fri Aug 6 01:22:31 2021 +0200
broadcom/qpu: define v3d_qpu_input, use on v3d_qpu_alu_instr
At this point it just tidy up a little the alu_instr structure.
But also serves to prepare the structure for new changes, as 7.x uses
raddr instead of mux, and it is just easier to add the raddr to the
new input structure.
Signed-off-by: Alejandro Piñeiro <[email protected]>
Signed-off-by: Iago Toral Quiroga <[email protected]>
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=224793491460e04d031aba3c8e79d7defec4c6d9
Author: Alejandro Piñeiro <[email protected]>
Date: Wed Aug 4 01:11:16 2021 +0200
broadcom/qpu: add v71 signal map
Compared with v41, the differences are:
* 14, 15, 29 and 30 are now about immediate a, b, c, d respectively
* 23 is now reserved. On v42 this was for rotate signals, that are
gone on v71.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d0c3667dd5b9ce8bda5ee6688009447a55923ee
Author: Alejandro Piñeiro <[email protected]>
Date: Thu Aug 5 00:50:12 2021 +0200
broadcom/compiler: add small_imm a/c/d on v3d_qpu_sig
small_imm_a, small_imm_c and small_imm_d added on top of the already
existing small_imm_b, as V3D 7.1 defines 4 small immediates, tied to
the 4 raddr. Note that this is only the definition, and just a inst
validation rule to check that are not used before v71. Any real use is
still pending.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5011e19c732b588e9d19af3109fa275f3a443e7
Author: Alejandro Piñeiro <[email protected]>
Date: Sun Sep 19 03:20:18 2021 +0200
broadcom/compiler: rename small_imm to small_imm_b
Current small_imm is associated with the "B" read address.
We do this change in advance for v71 support, where we will have 4
different small_imm (a/b/c/d), so we start with a renaming.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9bcefa964f69a3866fab0e03af539f2cb91178d
Author: Alejandro Piñeiro <[email protected]>
Date: Thu Aug 5 01:00:47 2021 +0200
broadcom/qpu: set V3D 7.x names for some waddr aliasing
V3D 7.x got rid of the accumulator, but still uses the values for
WADDR_R5 and WADDR_R5REP, so let's return a proper name and add some
aliases.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1c19d55ea73d6e3e234077c4660f78a1096c445
Author: Alejandro Piñeiro <[email protected]>
Date: Thu Aug 5 01:03:11 2021 +0200
broadcom/qpu: add comments on waddr not used on V3D 7.x
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=453b817cfd1c4bf33b6d2faa6ac81ce62b78a906
Author: Alejandro Piñeiro <[email protected]>
Date: Wed Nov 17 14:40:47 2021 +0100
broadcom/common: add some common v71 helpers
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=04f16574e66a150a012a42b45620b910ef0b544e
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Nov 9 08:50:51 2021 +0100
broadcom/common: retrieve V3D revision number
The subrev field from the hub ident3 register is bumped with every
hardware revision doing backwards incompatible changes so we want to
keep track of this.
Instead of modifying the 'ver' field info to acommodate subrev info,
which would require a lot of changes, simply add a new 'rev' field in
devinfo that we can use when we need to make changes based on the
revision number of a hardware release.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=52942aac0ef03297204a732169982d5cd4a4b0af
Author: Alejandro Piñeiro <[email protected]>
Date: Tue Jun 29 12:03:24 2021 +0200
broadcom/cle: update the packet definitions for new generation v71
Using as reference the spec for 7.1.5. This include totally new
packets, and redefine some that already existed on v42.
Full list:
* Add Depth Bounds Test Limits
* Redefine Tile Binning Mode Cfg
* Redefine Cfg Bits. There are some changes on the fields:
* Line Rasterization is now 1 bit size
* Depth Bounds Enable (that takes one of the bits of Line Rasterization)
* Early-Z/Early-Z updates enable bits (16-17) figure now as reserved.
* New Z-Clipping mode field
* Redefine Tile Rendering Mode Cfg (Common). Changes with respect to v42:
* New log2 tile height/width fields starting at bit 52/55
* Due those two news, end pad is smaller
* sub-id has now a size of 3. Bit 4 is reserved.
* Number of render targets: this field max value is now 7 (not
reflected on the xml).
* Maximum BPP is removed on v71 (now bits 40-41 are reserved)
* Depth Buffer disable: on bit 44
* Update Store Tile Buffer General
* Adding Cfg Render Target Part1/2/3 packets: they replace v4X "Tile
Rendering Mode Cfg (Color)" (real name "Rendering Configuration
(Render Targets Config)"), "Tile Rendering Mode Cfg (Clear Colors
Part1)", "Tile Rendering Mode Cfg (Clear Colors Part2)", and "Tile
Rendering Mode Cfg (Clear Colors Part3)". On those old versions,
the first packet is used to configure 4 render targets. Now that 8
are supported, invididual per-render-target are used.
* Update ZS clear values packet.
* Add new v71 output formats
* Define Clear Render Targets (Replaces Clear Tile Buffers from v42)
* Redefine GL Shader State Record. Changes copared with v42:
* Fields removed:
* "Coordinate shader has separate input and output VPM blocks"
(reserved bit now)
* "Vertex shader has separate input and output VPM blocks"
(reserved bit now)
* "Address of table of default attribute Values." (we needed to
change the start position for all the following fields)
* New field:
* "Never defer FEP depth writes to fragment shader auto Z writes
on scoreboard conflict"
* Redefine clipper xy scaling: Now it uses 1/64ths of pixels, instead
of 1/256ths
* Update texture shader state.
* Notice we don't use an address type for these fields in the XML
description. This is because the addresses are 64-bit aligned
(even though the PRM doesn't say it) which means the 6 LSB bits
are implicitly 0, but the fields are encoded before the 6th bit
of their starting byte, so we can't use the usual trick we do
with address types where the first 6 bits in the byte are
implicitly overwritten by other fields and we have to encode this
manually as a uint field. This would mean that if we had an
actual BO we would also need to add it manually to the job's
list, but since we don't have one, we don't have to do anything
about it.
* Add new RB_Swap field for texture shader state
* Document Cb/Cr addresses as uint fields in texture shader state
* Fixup Blend Config description: we now support 8 RTs.
* TMU config parameter 2 has new fields
* Add new clipper Z without guardband packet in v71
* Add enums for the Z clip modes accepted in v71
* Fix texture state array stride packing for V3D 7.1.5
Signed-off-by: Iago Toral Quiroga <[email protected]>
Signed-off-by: Alejandro Piñeiro <[email protected]>
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b2654949802cb2cb6371bc0480c1b4e79ccc76f
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Sep 28 13:16:49 2021 +0200
broadcom/simulator: reset CFG7 for compute dispatch in v71
This register is new in 7.x, it doesn't seem that we need to
do anything specific for now, but let's make sure it is reset
every time.
Reviewed-by: Alejandro Piñeiro <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d858332201fa30c32c4d8fd61217a4b66d16d0c6
Author: Alejandro Piñeiro <[email protected]>
Date: Mon Apr 26 00:02:21 2021 +0200
broadcom(cle,clif,common,simulator): add 7.1 version on the list of
versions to build
This adds 7.1 to the list of available V3D_VERSION, and first changes
on the simulator needed to get it working.
Note that we needed to touch all those 4 codebases because it is
needed if we want to use V3D_DEBUG=clif with the simulator, that it is
the easier way to see which packets a vulkan program is using.
About the simulator, this commit only handle the rename of some
registers. Any additional changes needed to get a proper support for
v71 will be handled them on following commits.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
