Thanks Schooner and Michael,
I followed the instructions through the setenv default -a; setenv ethaddr
ba:d0:4a:9c:4e:ce; saveenv; reset.
Now I get a little farther. Do I need to remove the 'quiet' in
extlinux.conf following the 'rootwait' so that I can see what is going on
in the starting kernel?
=~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2018.02.07 20:16:46
=~=~=~=~=~=~=~=~=~=~=~=
U-Boot SPL 2018.01-rc1-dirty (Jan 25 2018 - 15:56:14)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
drivers/ddr/altera/sequencer.c: Calibration complete
Trying to boot from MMC1
U-Boot 2018.01-rc1-dirty (Jan 25 2018 - 15:56:14 -0800)
CPU: Altera SoCFPGA Platform
FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT: SD/MMC Internal Transceiver (3.0V)
Watchdog enabled
I2C: ready
DRAM: 1 GiB
MMC: dwmmc0@ff704000: 0
In: serial
Out: serial
Err: serial
Model: Terasic DE10-Nano
Net: eth0: ethernet@ff702000
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:2...
Found /boot/extlinux/extlinux.conf
Retrieving file: /boot/extlinux/extlinux.conf
179 bytes read in 21 ms (7.8 KiB/s)
1: Linux 4.9.68-socfpga-r3
Retrieving file: /boot/vmlinuz-4.9.68-socfpga-r3
5455176 bytes read in 380 ms (13.7 MiB/s)
append: root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait quiet
Retrieving file: /boot/dtbs/4.9.68-socfpga-r3/socfpga_cyclone5_de10_nano.dtb
14997 bytes read in 45 ms (325.2 KiB/s)
## Flattened Device Tree blob at 02000000
Booting using the fdt blob at 0x2000000
reserving fdt memory region: addr=0 size=1000
Loading Device Tree to 03ff9000, end 03fffa94 ... OK
Starting kernel ...
*<My note: At this point it appears to start the process over >*
U-Boot SPL 2018.01-rc1-dirty (Jan 25 2018 - 15:56:14)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
drivers/ddr/altera/sequencer.c: Calibration complete
Trying to boot from MMC1
U-Boot 2018.01-rc1-dirty (Jan 25 2018 - 15:56:14 -0800)
CPU: Altera SoCFPGA Platform
FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT: SD/MMC Internal Transceiver (3.0V)
Watchdog enabled
I2C: ready
DRAM: 1 GiB
MMC: dwmmc0@ff704000: 0
In: serial
Out: serial
Err: serial
Model: Terasic DE10-Nano
Net: eth0: ethernet@ff702000
Hit any key to stop autoboot: 2 1 0
=>
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