Index: lib/Target/ARM/ARMJITInfo.cpp =================================================================== --- lib/Target/ARM/ARMJITInfo.cpp (revisão 41187) +++ lib/Target/ARM/ARMJITInfo.cpp (cópia de trabalho) @@ -21,12 +21,7 @@ using namespace llvm; void ARMJITInfo::replaceMachineCodeForFunction(void *Old, void *New) { - unsigned char *OldByte = (unsigned char *)Old; - *OldByte++ = 0xEA; // Emit B opcode. - unsigned *OldWord = (unsigned *)OldByte; - unsigned NewAddr = (intptr_t)New; - unsigned OldAddr = (intptr_t)OldWord; - *OldWord = NewAddr - OldAddr - 4; // Emit PC-relative addr of New code. + abort(); } /// JITCompilerFunction - This contains the address of the JIT function used to @@ -80,18 +75,16 @@ << ": Resolving call to function: " << TheVM->getFunctionReferencedName((void*)RetAddr) << "\n"; #endif + intptr_t Addr = RetAddr - 4; - // Sanity check to make sure this really is a branch and link instruction. - assert(((unsigned char*)RetAddr-1)[3] == 0xEB && "Not a branch and link instr!"); + intptr_t NewVal = (intptr_t)JITCompilerFunction((void*)Addr); - intptr_t NewVal = (intptr_t)JITCompilerFunction((void*)RetAddr); - // Rewrite the call target... so that we don't end up here every time we // execute the call. - *(intptr_t *)RetAddr = (intptr_t)(NewVal-RetAddr-4); + *(intptr_t *)Addr = NewVal; // Change the return address to reexecute the branch and link instruction... - *RetAddrLoc -= 1; + *RetAddrLoc -= 12; } TargetJITInfo::LazyResolverFn @@ -101,23 +94,25 @@ } void *ARMJITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) { - unsigned addr = (intptr_t)Fn-MCE.getCurrentPCValue()-4; + unsigned addr = (intptr_t)Fn; // If this is just a call to an external function, emit a branch instead of a // call. The code is the same except for one bit of the last instruction. if (Fn != (void*)(intptr_t)ARMCompilationCallback) { - MCE.startFunctionStub(4, 2); - MCE.emitByte(0xEA); // branch to the corresponding function addr - MCE.emitByte((unsigned char)(addr >> 0)); - MCE.emitByte((unsigned char)(addr >> 8)); - MCE.emitByte((unsigned char)(addr >> 16)); - return MCE.finishFunctionStub(0); + // branch to the corresponding function addr + // the stub is 8-byte size and 4-aligned + MCE.startFunctionStub(8, 4); + MCE.emitWordLE(0xE51FF004); // LDR PC, [PC,#-4] + MCE.emitWordLE(addr); // addr of function } else { - MCE.startFunctionStub(5, 2); - MCE.emitByte(0xEB); // branch and link to the corresponding function addr + // branch and link to the corresponding function addr + // the stub is 20-byte size and 4-aligned + MCE.startFunctionStub(20, 4); + MCE.emitWordLE(0xE92D4800); // STMFD SP!, [R11, LR] + MCE.emitWordLE(0xE28FE004); // ADD LR, PC, #4 + MCE.emitWordLE(0xE51FF004); // LDR PC, [PC,#-4] + MCE.emitWordLE(addr); // addr of function + MCE.emitWordLE(0xE8BD8800); // LDMFD SP!, [R11, PC] } - MCE.emitByte((unsigned char)(addr >> 0)); - MCE.emitByte((unsigned char)(addr >> 8)); - MCE.emitByte((unsigned char)(addr >> 16)); return MCE.finishFunctionStub(0); } @@ -132,15 +127,33 @@ intptr_t ResultPtr = (intptr_t)MR->getResultPointer(); switch ((ARM::RelocationType)MR->getRelocationType()) { case ARM::reloc_arm_relative: { - // PC relative relocation - *((unsigned*)RelocPos) += (unsigned)ResultPtr; + // It is necessary to calculate the correct PC relative value. We + // subtract the base addr from the target addr to form a byte offset. + ResultPtr = ResultPtr-(intptr_t)RelocPos-8; + // If the result is positive, set bit U(23) to 1. + if (ResultPtr >= 0) + *((unsigned*)RelocPos) |= 1 << 23; + else { + // otherwise, obtain the absolute value and set + // bit U(23) to 0. + ResultPtr *= -1; + *((unsigned*)RelocPos) &= 0xFF7FFFFF; + } + // set the immed value calculated + *((unsigned*)RelocPos) |= (unsigned)ResultPtr; + // set register Rn to PC + *((unsigned*)RelocPos) |= 0xF << 16; break; } - case ARM::reloc_arm_absolute: - break; case ARM::reloc_arm_branch: { - // relocation to b and bl instructions - ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2; + // It is necessary to calculate the correct value of signed_immed_24 + // field. We subtract the base addr from the target addr to form a + // byte offset, which must be inside the range -33554432 and +33554428. + // Then, we set the signed_immed_24 field of the instruction to bits + // [25:2] of the byte offset. More details ARM-ARM p. A4-11. + ResultPtr = ResultPtr-(intptr_t)RelocPos-8; + ResultPtr = (ResultPtr & 0x03FFFFFC) >> 2; + assert(ResultPtr >= -33554432 && ResultPtr <= 33554428); *((unsigned*)RelocPos) |= ResultPtr; break; } Index: lib/Target/ARM/ARMInstrInfo.td =================================================================== --- lib/Target/ARM/ARMInstrInfo.td (revisão 41187) +++ lib/Target/ARM/ARMInstrInfo.td (cópia de trabalho) @@ -342,33 +342,38 @@ def Pseudo : Format<1>; def MulFrm : Format<2>; -def Branch : Format<3>; -def BranchMisc : Format<4>; +def MulSMLAW : Format<3>; +def MulSMULW : Format<4>; +def MulSMLA : Format<5>; +def MulSMUL : Format<6>; +def Branch : Format<7>; +def BranchMisc : Format<8>; -def DPRdIm : Format<5>; -def DPRdReg : Format<6>; -def DPRdSoReg : Format<7>; -def DPRdMisc : Format<8>; -def DPRnIm : Format<9>; -def DPRnReg : Format<10>; -def DPRnSoReg : Format<11>; -def DPRIm : Format<12>; -def DPRReg : Format<13>; -def DPRSoReg : Format<14>; -def DPRImS : Format<15>; -def DPRRegS : Format<16>; -def DPRSoRegS : Format<17>; +def DPRdIm : Format<9>; +def DPRdReg : Format<10>; +def DPRdSoReg : Format<11>; +def DPRdMisc : Format<12>; +def DPRnIm : Format<13>; +def DPRnReg : Format<14>; +def DPRnSoReg : Format<15>; +def DPRIm : Format<16>; +def DPRReg : Format<17>; +def DPRSoReg : Format<18>; +def DPRImS : Format<19>; +def DPRRegS : Format<20>; +def DPRSoRegS : Format<21>; -def LdFrm : Format<18>; -def StFrm : Format<19>; +def LdFrm : Format<22>; +def StFrm : Format<23>; -def ArithMisc : Format<20>; -def ThumbFrm : Format<21>; -def VFPFrm : Format<22>; +def ArithMisc : Format<24>; +def ThumbFrm : Format<25>; +def VFPFrm : Format<26>; //===----------------------------------------------------------------------===// + // ARM Instruction templates. // @@ -776,7 +781,7 @@ // FIXME: should be able to write a pattern for ARMBrcond, but can't use // a two-value operand where a dag node expects two operands. :( - def Bcc : AI<0x0, (outs), (ins brtarget:$target), Branch, + def Bcc : AI<0xA, (outs), (ins brtarget:$target), Branch, "b", " $target", [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>; } @@ -815,7 +820,7 @@ [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; // Load doubleword -def LDRD : AI3<0x0, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm, +def LDRD : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm, "ldr", "d $dst, $addr", []>, Requires<[IsARM, HasV5T]>; @@ -877,7 +882,7 @@ [(truncstorei8 GPR:$src, addrmode2:$addr)]>; // Store doubleword -def STRD : AI3<0x0, (outs), (ins GPR:$src, addrmode3:$addr), StFrm, +def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm, "str", "d $src, $addr", []>, Requires<[IsARM, HasV5T]>; @@ -1125,76 +1130,86 @@ [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>, Requires<[IsARM, HasV6]>; -multiclass AI_smul opcod, string opc, PatFrag opnode> { - def BB : AI { + def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL, !strconcat(opc, "bb"), " $dst, $a, $b", [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), (sext_inreg GPR:$b, i16)))]>, Requires<[IsARM, HasV5TE]>; - def BT : AI, Requires<[IsARM, HasV5TE]>; - def TB : AI, Requires<[IsARM, HasV5TE]>; - def TT : AI, Requires<[IsARM, HasV5TE]>; - def WB : AI, Requires<[IsARM, HasV5TE]>; - def WT : AI, Requires<[IsARM, HasV5TE]>; } -multiclass AI_smla opcod, string opc, PatFrag opnode> { - def BB : AI { + def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA, !strconcat(opc, "bb"), " $dst, $a, $b, $acc", [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), (sext_inreg GPR:$b, i16))))]>, Requires<[IsARM, HasV5TE]>; - def BT : AI, Requires<[IsARM, HasV5TE]>; - def TB : AI, Requires<[IsARM, HasV5TE]>; - def TT : AI, Requires<[IsARM, HasV5TE]>; - def WB : AI, Requires<[IsARM, HasV5TE]>; - def WT : AI, Requires<[IsARM, HasV5TE]>; } -defm SMUL : AI_smul<0x0, "smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; -defm SMLA : AI_smla<0x0, "smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; +defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; +defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; // TODO: Halfword multiple accumulate long: SMLAL // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD Index: lib/Target/ARM/ARMCodeEmitter.cpp =================================================================== --- lib/Target/ARM/ARMCodeEmitter.cpp (revisão 41187) +++ lib/Target/ARM/ARMCodeEmitter.cpp (cópia de trabalho) @@ -54,9 +54,9 @@ } void emitInstruction(const MachineInstr &MI); - unsigned getBinaryCodeForInstr(const MachineInstr &MI); int getMachineOpValue(const MachineInstr &MI, unsigned OpIndex); unsigned getBaseOpcodeFor(const TargetInstrDescriptor *TID); + unsigned getBinaryCodeForInstr(const MachineInstr &MI); void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub); void emitExternalSymbolAddress(const char *ES, unsigned Reloc); @@ -64,6 +64,8 @@ int Disp = 0, unsigned PCAdj = 0 ); void emitJumpTableAddress(unsigned JTI, unsigned Reloc, unsigned PCAdj = 0); + void emitGlobalConstant(const Constant *CV); + void emitMachineBasicBlock(MachineBasicBlock *BB); private: int getShiftOp(const MachineOperand &MO); @@ -100,10 +102,13 @@ return false; } +/// getBaseOpcodeFor - Return the opcode value unsigned Emitter::getBaseOpcodeFor(const TargetInstrDescriptor *TID) { return (TID->TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift; } +/// getShiftOp - Verify which is the shift opcode (bit[6:5]) of the +/// machine operand. int Emitter::getShiftOp(const MachineOperand &MO) { unsigned ShiftOp = 0x0; switch(ARM_AM::getAM2ShiftOpc(MO.getImmedValue())) { @@ -133,20 +138,18 @@ rv = ARMRegisterInfo::getRegisterNumbering(MO.getReg()); } else if (MO.isImmediate()) { rv = MO.getImmedValue(); - } else if (MO.isGlobalAddress() || MO.isExternalSymbol() || - MO.isConstantPoolIndex() || MO.isJumpTableIndex()) { + } else if (MO.isGlobalAddress()) { + emitGlobalAddressForCall(MO.getGlobal(), false); + } else if (MO.isExternalSymbol()) { + emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative); + } else if (MO.isConstantPoolIndex()) { + emitConstPoolAddress(MO.getConstantPoolIndex(), ARM::reloc_arm_relative); + } else if (MO.isJumpTableIndex()) { + emitJumpTableAddress(MO.getJumpTableIndex(), ARM::reloc_arm_relative); + } else if (MO.isMachineBasicBlock()) { + emitMachineBasicBlock(MO.getMachineBasicBlock()); + } - if (MO.isGlobalAddress()) { - emitGlobalAddressForCall(MO.getGlobal(), true); - } else if (MO.isExternalSymbol()) { - emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative); - } else if (MO.isConstantPoolIndex()) { - emitConstPoolAddress(MO.getConstantPoolIndex(), ARM::reloc_arm_relative); - } else if (MO.isJumpTableIndex()) { - emitJumpTableAddress(MO.getJumpTableIndex(), ARM::reloc_arm_relative); - } - - } return rv; } @@ -186,8 +189,12 @@ Reloc, JTI, PCAdj)); } +/// emitMachineBasicBlock - Emit the specified address basic block. +void Emitter::emitMachineBasicBlock(MachineBasicBlock *BB) { + MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), + ARM::reloc_arm_branch, BB)); +} - void Emitter::emitInstruction(const MachineInstr &MI) { NumEmitted++; // Keep track of the # of mi's emitted MCE.emitWordLE(getBinaryCodeForInstr(MI)); @@ -196,6 +203,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) { const TargetInstrDescriptor *Desc = MI.getInstrDescriptor(); const unsigned opcode = MI.getOpcode(); + // initial instruction mask unsigned Value = 0xE0000000; unsigned op; @@ -204,10 +212,11 @@ switch(Desc->TSFlags & ARMII::FormMask) { default: { assert(0 && "Unknown instruction subtype!"); + // treat special instruction CLZ if(opcode == ARM::CLZ) { // set first operand op = getMachineOpValue(MI,0); - Value |= op << 12; + Value |= op << ARMII::RegRdShift; // set second operand op = getMachineOpValue(MI,1); @@ -215,9 +224,51 @@ } break; } + case ARMII::MulSMLAW: + case ARMII::MulSMULW: + // set bit W(21) + Value |= 1 << 21; + case ARMII::MulSMLA: + case ARMII::MulSMUL: { + // set bit W(21) + Value |= 1 << 24; + + // set opcode (bit[7:4]). For more information, see ARM-ARM page A3-31 + // SMLA - 1yx0 + // SMLAW - 1y00 + // SMULW - 1y10 + // SMUL - 1yx0 + unsigned char BaseOpcode = getBaseOpcodeFor(Desc); + Value |= BaseOpcode << 4; + + unsigned Format = (Desc->TSFlags & ARMII::FormMask); + if (Format == ARMII::MulSMUL) + Value |= 1 << 22; + + // set first operand + op = getMachineOpValue(MI,0); + Value |= op << ARMII::RegRnShift; + + // set second operand + op = getMachineOpValue(MI,1); + Value |= op; + + // set third operand + op = getMachineOpValue(MI,2); + Value |= op << ARMII::RegRsShift; + + // instructions SMLA and SMLAW have a fourth operand + if (Format != ARMII::MulSMULW && Format != ARMII::MulSMUL) { + op = getMachineOpValue(MI,3); + Value |= op << ARMII::RegRdShift; + } + + break; + } case ARMII::MulFrm: { + // bit[7:4] is always 9 Value |= 9 << 4; - + // set opcode (bit[23:20]) unsigned char BaseOpcode = getBaseOpcodeFor(Desc); Value |= BaseOpcode << 20; @@ -226,40 +277,53 @@ // set first operand op = getMachineOpValue(MI,0); - Value |= op << (isMUL || isMLA ? 16 : 12); + Value |= op << (isMUL || isMLA ? ARMII::RegRnShift : ARMII::RegRdShift); // set second operand op = getMachineOpValue(MI,1); - Value |= op << (isMUL || isMLA ? 0 : 16); + Value |= op << (isMUL || isMLA ? 0 : ARMII::RegRnShift); // set third operand op = getMachineOpValue(MI,2); - Value |= op << (isMUL || isMLA ? 8 : 0); + Value |= op << (isMUL || isMLA ? ARMII::RegRsShift : 0); + // multiply instructions (except MUL), have a fourth operand if (!isMUL) { op = getMachineOpValue(MI,3); - Value |= op << (isMLA ? 12 : 8); + Value |= op << (isMLA ? ARMII::RegRdShift : ARMII::RegRsShift); } break; } case ARMII::Branch: { + // set opcode (bit[27:24]) unsigned BaseOpcode = getBaseOpcodeFor(Desc); Value |= BaseOpcode << 24; + // set signed_immed_24 field op = getMachineOpValue(MI,0); Value |= op; + // if it is a conditional branch, set cond field + if (opcode == ARM::Bcc) { + op = getMachineOpValue(MI,1); + Value &= 0x0FFFFFFF; // clear conditional field + Value |= op << 28; // set conditional field + } + break; } case ARMII::BranchMisc: { + // set opcode (bit[7:4]) unsigned char BaseOpcode = getBaseOpcodeFor(Desc); Value |= BaseOpcode << 4; + // set bit[27:24] to 1, set bit[23:20] to 2 and set bit[19:8] to 0xFFF Value |= 0x12fff << 8; if (opcode == ARM::BX_RET) - op = 0xe; + op = 0xe; // the return register is LR else + // otherwise, set the return register op = getMachineOpValue(MI,0); Value |= op; @@ -272,12 +336,15 @@ break; } case ARMII::AddrMode1: { + // set opcode (bit[24:21]) of data-processing instructions unsigned char BaseOpcode = getBaseOpcodeFor(Desc); Value |= BaseOpcode << 21; + // treat 3 special instructions: MOVsra_flag, MOVsrl_flag and + // MOVrx. unsigned Format = (Desc->TSFlags & ARMII::FormMask); if (Format == ARMII::DPRdMisc) { - Value |= getMachineOpValue(MI,0) << 12; + Value |= getMachineOpValue(MI,0) << ARMII::RegRdShift; Value |= getMachineOpValue(MI,1); switch(opcode) { case ARM::MOVsra_flag: { @@ -298,20 +365,26 @@ break; } - bool IsDataProcessing3 = false; - - if (Format == ARMII::DPRImS || Format == ARMII::DPRRegS || - Format == ARMII::DPRSoRegS) { - Value |= 1 << 20; - IsDataProcessing3 = true; - } - + // Data processing operand instructions has 3 possible encodings (for more + // information, see ARM-ARM page A3-10): + // 1. , + // 2. , + // 3. ,, bool IsDataProcessing1 = Format == ARMII::DPRdIm || Format == ARMII::DPRdReg || Format == ARMII::DPRdSoReg; bool IsDataProcessing2 = Format == ARMII::DPRnIm || Format == ARMII::DPRnReg || Format == ARMII::DPRnSoReg; + bool IsDataProcessing3 = false; + + // set bit S(20) + if (Format == ARMII::DPRImS || Format == ARMII::DPRRegS || + Format == ARMII::DPRSoRegS || IsDataProcessing2) { + Value |= 1 << ARMII::S_BitShift; + IsDataProcessing3 = !IsDataProcessing2; + } + IsDataProcessing3 = Format == ARMII::DPRIm || Format == ARMII::DPRReg || Format == ARMII::DPRSoReg || @@ -320,22 +393,24 @@ // set first operand op = getMachineOpValue(MI,0); if (IsDataProcessing1 || IsDataProcessing3) { - Value |= op << 12; + Value |= op << ARMII::RegRdShift; } else if (IsDataProcessing2) { - Value |= op << 16; + Value |= op << ARMII::RegRnShift; } + // set second operand of data processing #3 instructions if (IsDataProcessing3) { op = getMachineOpValue(MI,1); - Value |= op << 16; + Value |= op << ARMII::RegRnShift; } unsigned OperandIndex = IsDataProcessing3 ? 2 : 1; - // set shift operand switch (Format) { case ARMII::DPRdIm: case ARMII::DPRnIm: case ARMII::DPRIm: case ARMII::DPRImS: { - Value |= 1 << 25; + // set bit I(25) to identify this is the immediate form of + Value |= 1 << ARMII::I_BitShift; + // set immed_8 field const MachineOperand &MO = MI.getOperand(OperandIndex); op = ARM_AM::getSOImmVal(MO.getImmedValue()); Value |= op; @@ -344,6 +419,7 @@ } case ARMII::DPRdReg: case ARMII::DPRnReg: case ARMII::DPRReg: case ARMII::DPRRegS: { + // set last operand (register Rm) op = getMachineOpValue(MI,OperandIndex); Value |= op; @@ -351,12 +427,20 @@ } case ARMII::DPRdSoReg: case ARMII::DPRnSoReg: case ARMII::DPRSoReg: case ARMII::DPRSoRegS: { + // set last operand (register Rm) op = getMachineOpValue(MI,OperandIndex); Value |= op; const MachineOperand &MO1 = MI.getOperand(OperandIndex + 1); const MachineOperand &MO2 = MI.getOperand(OperandIndex + 2); + // identify it the instr is in immed or register shifts encoding bool IsShiftByRegister = MO1.getReg() > 0; + // set shift operand (bit[6:4]). + // ASR - 101 if it is in register shifts encoding; 100, otherwise. + // LSL - 001 if it is in register shifts encoding; 000, otherwise. + // LSR - 011 if it is in register shifts encoding; 010, otherwise. + // ROR - 111 if it is in register shifts encoding; 110, otherwise. + // RRX - 110 and bit[11:7] clear. switch(ARM_AM::getSORegShOp(MO2.getImmedValue())) { default: assert(0 && "Unknown shift opc!"); case ARM_AM::asr: { @@ -390,13 +474,16 @@ break; } } + // set the field related to shift operations (except rrx). if(ARM_AM::getSORegShOp(MO2.getImmedValue()) != ARM_AM::rrx) if(IsShiftByRegister) { + // set the value of bit[11:8] (register Rs). assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); op = ARMRegisterInfo::getRegisterNumbering(MO1.getReg()); assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); - Value |= op << 8; + Value |= op << ARMII::RegRsShift; } else { + // set the value of bit [11:7] (shift_immed field). op = ARM_AM::getSORegOffset(MO2.getImm()); Value |= op << 7; } @@ -409,83 +496,107 @@ break; } case ARMII::AddrMode2: { + // bit 26 is always 1 Value |= 1 << 26; unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask); + // if the instruction uses offset addressing or pre-indexed addressing, + // set bit P(24) to 1 if (Index == ARMII::IndexModePre || Index == 0) - Value |= 1 << 24; + Value |= 1 << ARMII::IndexShift; + // if the instruction uses post-indexed addressing, set bit W(21) to 1 if (Index == ARMII::IndexModePre) Value |= 1 << 21; unsigned Format = (Desc->TSFlags & ARMII::FormMask); + // If it is a load instruction (except LDRD), set bit L(20) to 1 if (Format == ARMII::LdFrm) - Value |= 1 << 20; + Value |= 1 << ARMII::L_BitShift; + // set bit B(22) unsigned BitByte = getBaseOpcodeFor(Desc); Value |= BitByte << 22; // set first operand op = getMachineOpValue(MI,0); - Value |= op << 12; + Value |= op << ARMII::RegRdShift; - // addressing mode + // set second operand op = getMachineOpValue(MI,1); - Value |= op << 16; + Value |= op << ARMII::RegRnShift; const MachineOperand &MO2 = MI.getOperand(2); const MachineOperand &MO3 = MI.getOperand(3); - Value |= (ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) << 23; + // set bit U(23) according to signal of immed value (positive or negative) + Value |= (ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) << + ARMII::U_BitShift; if (!MO2.getReg()) { // is immediate if (ARM_AM::getAM2Offset(MO3.getImm())) + // set the value of offset_12 field Value |= ARM_AM::getAM2Offset(MO3.getImm()); break; } - Value |= 1 << 25; + // set bit I(25), because this is not in immediate enconding. + Value |= 1 << ARMII::I_BitShift; assert(MRegisterInfo::isPhysicalRegister(MO2.getReg())); + // set bit[3:0] to the corresponding Rm register Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); + // if this instr is in scaled register offset/index instruction, set + // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) { unsigned ShiftOp = getShiftOp(MO3); - Value |= ShiftOp << 5; - Value |= ShImm << 7; + Value |= ShiftOp << 5; // shift + Value |= ShImm << 7; // shift_immed } break; } case ARMII::AddrMode3: { + unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask); + // if the instruction uses offset addressing or pre-indexed addressing, + // set bit P(24) to 1 if (Index == ARMII::IndexModePre || Index == 0) - Value |= 1 << 24; + Value |= 1 << ARMII::IndexShift; unsigned Format = (Desc->TSFlags & ARMII::FormMask); - if (Format == ARMII::LdFrm) - Value |= 1 << 20; + // If it is a load instruction (except LDRD), set bit L(20) to 1 + if (Format == ARMII::LdFrm && opcode != ARM::LDRD) + Value |= 1 << ARMII::L_BitShift; + // bit[7:4] is the opcode of this instruction class (bits S and H). unsigned char BaseOpcode = getBaseOpcodeFor(Desc); Value |= BaseOpcode << 4; // set first operand op = getMachineOpValue(MI,0); - Value |= op << 12; + Value |= op << ARMII::RegRdShift; - // addressing mode + // set second operand op = getMachineOpValue(MI,1); - Value |= op << 16; + Value |= op << ARMII::RegRnShift; const MachineOperand &MO2 = MI.getOperand(2); const MachineOperand &MO3 = MI.getOperand(3); - Value |= (ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) << 23; + // set bit U(23) according to signal of immed value (positive or negative) + Value |= (ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) << + ARMII::U_BitShift; + // if this instr is in register offset/index encoding, set bit[3:0] + // to the corresponding Rm register. if (MO2.getReg()) { Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); break; } + // if this instr is in immediate offset/index encoding, set bit 22 to 1 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) { Value |= 1 << 22; + // set operands Value |= (ImmOffs >> 4) << 8; // immedH Value |= (ImmOffs & ~0xF); // immedL } @@ -493,30 +604,36 @@ break; } case ARMII::AddrMode4: { + // bit 27 is always 1 Value |= 1 << 27; unsigned Format = (Desc->TSFlags & ARMII::FormMask); + // if it is a load instr, set bit L(20) to 1 if (Format == ARMII::LdFrm) - Value |= 1 << 20; + Value |= 1 << ARMII::L_BitShift; unsigned OpIndex = 0; // set first operand op = getMachineOpValue(MI,OpIndex); - Value |= op << 16; + Value |= op << ARMII::RegRnShift; - // set addressing mode + // set addressing mode by modifying bits U(23) and P(24) + // IA - Increment after - bit U = 1 and bit P = 0 + // IB - Increment before - bit U = 1 and bit P = 1 + // DA - Decrement after - bit U = 0 and bit P = 0 + // DB - Decrement before - bit U = 0 and bit P = 1 const MachineOperand &MO = MI.getOperand(OpIndex + 1); ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm()); switch(Mode) { default: assert(0 && "Unknown addressing sub-mode!"); case ARM_AM::ia: Value |= 0x1 << 23; break; - case ARM_AM::ib: Value |= 0x2 << 23; break; + case ARM_AM::ib: Value |= 0x3 << 23; break; case ARM_AM::da: break; case ARM_AM::db: Value |= 0x1 << 24; break; } - // set flag W + // set bit W(21) if (ARM_AM::getAM4WBFlag(MO.getImm())) Value |= 0x1 << 21; Index: lib/Target/ARM/ARMInstrInfo.h =================================================================== --- lib/Target/ARM/ARMInstrInfo.h (revisão 41187) +++ lib/Target/ARM/ARMInstrInfo.h (cópia de trabalho) @@ -68,48 +68,61 @@ FormShift = 13, FormMask = 31 << FormShift, -// Pseudo instructions + // Pseudo instructions Pseudo = 1 << FormShift, -// Multiply instructions + // Multiply instructions MulFrm = 2 << FormShift, + MulSMLAW = 3 << FormShift, + MulSMULW = 4 << FormShift, + MulSMLA = 5 << FormShift, + MulSMUL = 6 << FormShift, -// Branch instructions - Branch = 3 << FormShift, - BranchMisc = 4 << FormShift, + // Branch instructions + Branch = 7 << FormShift, + BranchMisc = 8 << FormShift, -// Data Processing instructions - DPRdIm = 5 << FormShift, - DPRdReg = 6 << FormShift, - DPRdSoReg = 7 << FormShift, - DPRdMisc = 8 << FormShift, + // Data Processing instructions + DPRdIm = 9 << FormShift, + DPRdReg = 10 << FormShift, + DPRdSoReg = 11 << FormShift, + DPRdMisc = 12 << FormShift, - DPRnIm = 9 << FormShift, - DPRnReg = 10 << FormShift, - DPRnSoReg = 11 << FormShift, + DPRnIm = 13 << FormShift, + DPRnReg = 14 << FormShift, + DPRnSoReg = 15 << FormShift, - DPRIm = 12 << FormShift, - DPRReg = 13 << FormShift, - DPRSoReg = 14 << FormShift, + DPRIm = 16 << FormShift, + DPRReg = 17 << FormShift, + DPRSoReg = 18 << FormShift, - DPRImS = 15 << FormShift, - DPRRegS = 16 << FormShift, - DPRSoRegS = 17 << FormShift, + DPRImS = 19 << FormShift, + DPRRegS = 20 << FormShift, + DPRSoRegS = 21 << FormShift, -// Load and Store - LdFrm = 18 << FormShift, - StFrm = 19 << FormShift, + // Load and Store + LdFrm = 22 << FormShift, + StFrm = 23 << FormShift, -// Miscellaneous arithmetic instructions - ArithMisc = 20 << FormShift, + // Miscellaneous arithmetic instructions + ArithMisc = 24 << FormShift, -// Thumb format - ThumbFrm = 21 << FormShift, + // Thumb format + ThumbFrm = 25 << FormShift, -// VFP format - VPFFrm = 22 << FormShift - + // VFP format + VPFFrm = 26 << FormShift, + // Field shifts - such shifts are used to set field while generating + // machine instructions. + RegRsShift = 8, + RegRdShift = 12, + RegRnShift = 16, + L_BitShift = 20, + S_BitShift = 20, + U_BitShift = 23, + IndexShift = 24, + I_BitShift = 25 }; } Index: lib/Target/ARM/ARMRelocations.h =================================================================== --- lib/Target/ARM/ARMRelocations.h (revisão 41187) +++ lib/Target/ARM/ARMRelocations.h (cópia de trabalho) @@ -21,8 +21,6 @@ enum RelocationType { reloc_arm_relative, - reloc_arm_absolute, - reloc_arm_branch }; }