| Issue |
150304
|
| Summary |
RISC-V assembler should accept compressed shift hints with 0 immediates
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
Timmmm
|
Currently if you try to assemble any of these instructions Clang will complain:
```
asm.s:49864:13: error: immediate must be an integer in the range [1, 63]
c.srli x14, 0x0
^
asm.s:50440:12: error: immediate must be an integer in the range [1, 63]
c.srai x9, 0x0
^
asm.s:188:12: error: immediate must be an integer in the range [1, 63]
c.slli x1, 0x0
^
```
These compressed shift instructions with a 0 immediate are HINTs, but I don't think that means you shouldn't be allowed to assemble them. You can assemble `c.nop` hints for example `c.nop 1`.
There probably isn't a practical use for this yet seeing as no meaning has been assigned to these hints (they are [designated for custom use](https://riscv-specs.timhutt.co.uk/spec/riscv-isa-release-ffbb6fa-2025-07-17/riscv-unprivileged.html#rvc-t-hints)), but it would be nice if there was some valid syntax for representing them.
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